Lines Matching defs:NewReg

303 // be replaced by NewReg. Return true if any of their parent instructions may
308 // the two-address instruction also defines NewReg, as may happen with
312 // both NewReg and AntiDepReg covers it.
316 unsigned NewReg)
322 // operands, in case they may be assigned to NewReg. In this case antidep
327 // Handle cases in which this instructions defines NewReg.
332 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
336 CheckOper.getReg() != NewReg)
339 // Don't allow the instruction to define NewReg and AntiDepReg.
345 // NewReg
349 // Don't allow inline asm to define NewReg at all. Who know what it's
368 unsigned NewReg = Order[i];
370 if (NewReg == AntiDepReg) continue;
374 if (NewReg == LastNewReg) continue;
375 // If any instructions that define AntiDepReg also define the NewReg, it's
378 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
379 // If NewReg is dead and NewReg's most recent def is not before
380 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
383 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
384 && "Kill and Def maps aren't consistent for NewReg!");
385 if (KillIndices[NewReg] != ~0u ||
386 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
387 KillIndices[AntiDepReg] > DefIndices[NewReg])
389 // If NewReg overlaps any of the forbidden registers, we can't use it.
393 if (TRI->regsOverlap(NewReg, *it)) {
398 return NewReg;
606 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
613 << " using " << TRI->getName(NewReg) << "!\n");
619 Q->second->setReg(NewReg);
628 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
634 Classes[NewReg] = Classes[AntiDepReg];
635 DefIndices[NewReg] = DefIndices[AntiDepReg];
636 KillIndices[NewReg] = KillIndices[AntiDepReg];
637 assert(((KillIndices[NewReg] == ~0u) !=
638 (DefIndices[NewReg] == ~0u)) &&
639 "Kill and Def maps aren't consistent for NewReg!");
649 LastNewReg[AntiDepReg] = NewReg;