config/ia64/ia64.c

115 /* Variables which are this size or smaller are put in the sdata/sbss
706      the validity of the underlying address, which should have been
1156    May return an insn which is to be emitted after the moves.  */
1220 		/* Reversal requires a pre-increment, which can only
1378    (subreg:XF (reg:TI)), which we got from a union containing a long double.
1403 /* Expand the movxf or movrf pattern (MODE says which) with the given
1553   /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
2126   /* Because of the volatile mem read, we get an ld.acq, which is the
2186   /* Variable tracking should be run after all optimizations which change order
2400   /* Discover which registers need spilling, and how much room that
2402      which will always wind up on the stack.  */
2577      if we are a leaf function, there's no one to which we need to provide
2626 	 in which case we store through the 16 byte save area.  */
2662   rtx init_after;		/* point at which to emit initializations */
2742      CFA 0, which may allow the real iterator to be initialized lower,
2795 	 eliminated by copyprop_hardreg_forward, which makes this
2796 	 insn garbage, which runs afoul of the sanity check in
2946      for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3086      bits from varargs, which we don't care about.  */
3826    for the last named argument which has type TYPE and mode MODE.
4671 	const char *which;
4683 	      which = ".spnt";
4685 	      which = ".dpnt";
4688 	      which = ".dptk";
4690 	      which = ".sptk";
4693 	  which = ".sptk";
4695 	  which = ".dptk";
4697 	fputs (which, file);
4792          which normally involves copies.  Plus there's the latency
4951 	 both of which are equiv to the same constant, and both which need
4953 	 changes depending on the path length, which means the qty_first_reg
5202 /* This is used for volatile asms which may require a stop bit immediately
5244    in which case we don't need another stop bit.  Without this,
5270 /* Update *RWS for REGNO, which is being written by the current instruction,
5424 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5439 	 (1) The destination is (pc), in which case this is a branch,
5441 	 (2) The destination is ar.lc, in which case this is a
5443 	 (3) The destination is an fp register, in which case this is
5445 	 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
5607 	 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6008    instruction scheduling pass has been run which has already
6189 /* The following array element values are cycles on which the
6294   /* Before reload, which_alternative is not set, which means that
7214 /* The following page contains abstract data `bundle states' which are
7594    because undocumented anomaly in McKinley derived cores which can
7744    reject some decisions which cannot improve the solution and
7797   /* Shift cycle mark if it is put on insn which could be ignored.  */
8071 	  /* We found a MM-insn which needs additional cycles.  */
8078 	       which the MM-insn is placed and the position of the
8411       /* Skip p0, which may be thought to be live due to (reg:DI p0)
8619 	 which in turn makes it possible to restart a system call after
8631       /* Likewise for ar.pfs, which is used by br.ret.  */
8672    types which can't go in sdata/sbss.  */
8798    which result in emitting an assembly directive required for unwinding.  */
9333      use them instead of _U_Qfcmp, which doesn't work the way we