binutils/opcodes/ia64-opc-m.c

24 #define M0	IA64_TYPE_M, 0
80     {"chk.a.nc",	M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY},
81     {"chk.a.clr",	M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY},
82     {"chk.a.nc",	M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY},
83     {"chk.a.clr",	M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY},
85     {"invala",		M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY},
86     {"fwb",		M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY},
87     {"mf",		M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY},
88     {"mf.a",		M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY},
89     {"srlz.d",		M0, OpX3X4X2 (0, 0, 0, 3), {}, EMPTY},
90     {"srlz.i",		M0, OpX3X4X2 (0, 0, 1, 3), {}, EMPTY},
91     {"sync.i",		M0, OpX3X4X2 (0, 0, 3, 3), {}, EMPTY},
92     {"flushrs",		M0, OpX3X4X2 (0, 0, 0xc, 0), {}, FIRST | NO_PRED, 0, NULL},
93     {"loadrs",		M0, OpX3X4X2 (0, 0, 0xa, 0), {}, FIRST | NO_PRED, 0, NULL},
94     {"invala.e",	M0, OpX3X4X2 (0, 0, 2, 1), {R1}, EMPTY},
95     {"invala.e",	M0, OpX3X4X2 (0, 0, 3, 1), {F1}, EMPTY},
98     {"break.m",		M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}, EMPTY},
99     {"nop.m",		M0, OpX3X4X2Y (0, 0, 1, 0, 0), {IMMU21}, EMPTY},
100     {"hint.m",		M0, OpX3X4X2Y (0, 0, 1, 0, 1), {IMMU21}, EMPTY},
102     {"sum",		M0, OpX3X4 (0, 0, 4), {IMMU24}, EMPTY},
103     {"rum",		M0, OpX3X4 (0, 0, 5), {IMMU24}, EMPTY},
104     {"ssm",		M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV, 0, NULL},
105     {"rsm",		M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV, 0, NULL},
123     {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY},
124     {"probe.r.fault",  M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY},
125     {"probe.w.fault",  M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY},
126     {"itc.d",	M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV, 0, NULL},
127     {"itc.i",	M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV, 0, NULL},
148     {"ptc.l",	M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL},
149     {"ptc.g",	M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL},
150     {"ptc.ga",	M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL},
151     {"ptr.d",	M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV, 0, NULL},
152     {"ptr.i",	M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV, 0, NULL},
159     {"chk.s.m",	M0, OpX3 (1, 1), {R2, TGT25b}, EMPTY},
160     {"chk.s",	M0, OpX3 (1, 3), {F2, TGT25b}, EMPTY},
162     {"fc",	M0, OpX3X6bX7 (1, 0, 0x30, 0), {R3}, EMPTY},
163     {"fc.i",	M0, OpX3X6bX7 (1, 0, 0x30, 1), {R3}, EMPTY},
164     {"ptc.e",	M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL},
932     {"lfetch",			M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}, EMPTY},
933     {"lfetch.nt1",		M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}, EMPTY},
934     {"lfetch.nt2",		M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}, EMPTY},
935     {"lfetch.nta",		M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}, EMPTY},
936     {"lfetch.excl",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}, EMPTY},
937     {"lfetch.excl.nt1",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}, EMPTY},
938     {"lfetch.excl.nt2",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}, EMPTY},
939     {"lfetch.excl.nta",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}, EMPTY},
940     {"lfetch.fault",		M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}, EMPTY},
941     {"lfetch.fault.nt1",	M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}, EMPTY},
942     {"lfetch.fault.nt2",	M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}, EMPTY},
943     {"lfetch.fault.nta",	M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}, EMPTY},
944     {"lfetch.fault.excl",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}, EMPTY},
945     {"lfetch.fault.excl.nt1",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}, EMPTY},
946     {"lfetch.fault.excl.nt2",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}, EMPTY},
947     {"lfetch.fault.excl.nta",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}, EMPTY},
950 #define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC, 0, NULL
1069 #define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC, 0, NULL
1091 #undef M0