Lines Matching defs:link
490 * Programs a link's PCIe SWAP regions from the link's IO and MEM address
494 xlp_pcib_hardware_swap_enable(int node, int link)
501 pcieoffset = XLP_IO_PCIE_OFFSET(node, link);
507 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link);
510 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
513 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
516 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
524 int node, link;
530 for (link = 0; link < 4; link++)
531 xlp_pcib_hardware_swap_enable(node, link);
546 * XLS PCIe can have upto 4 links, and each link has its on IRQ
547 * Find the link on which the device is on
572 int i, link;
575 * Each link has 32 MSIs that can be allocated, but for now
576 * we only support one device per link.
578 * bridges on the PCIe link.
580 link = xlp_pcie_link(pcib, dev);
581 if (link == -1)
589 irqs[i] = 64 + link * 32 + i;
677 * link, and assign the link interrupt to the device interrupt
680 int node, val, link;
688 link = xlpirq / 32;
689 base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link));
819 int irt, link;
838 * For PCIe links, return link IRT, for other SoC devices
853 link = xlp_pcie_link(bus, dev);
854 irt = xlp_pcie_link_irt(link);