nlm/hal/fmn.c

73  * Calculates the base, start & end and returns the same for a
116  *   | base ptr       |
139 void nlm_cms_setup_credits(uint64_t base, int destid, int srcid, int credit)
144 	nlm_write_cms_reg(base, CMS_OUTPUTQ_CREDIT_CFG, val);
149  * base		- CMS module base address for this node.
156 int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base,
166 	queue_config = nlm_read_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)));
175 	nlm_write_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)),queue_config);
180 uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid)
182 	return nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
185 void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val)
189 	rdval = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
191 	nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), rdval);
194 void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type,
199 	val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
206 	nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
209 void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type,
214 	val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
221 	nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
225 int nlm_cms_outputq_intr_check(uint64_t base, int qid)
228 	val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
233 void nlm_cms_outputq_clr_intr(uint64_t base, int qid)
236 	val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
238 	nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
241 void nlm_cms_illegal_dst_error_intr(uint64_t base, int en)
245 	val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
247 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
250 void nlm_cms_timeout_error_intr(uint64_t base, int en)
254 	val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
256 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
259 void nlm_cms_biu_error_resp_intr(uint64_t base, int en)
263 	val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
265 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
268 void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en)
272 	val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
274 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
277 void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en)
281 	val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
283 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
286 void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en)
290 	val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
292 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
295 void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en)
299 	val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
301 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
304 uint64_t nlm_cms_network_error_status(uint64_t base)
306 	return nlm_read_cms_reg(base, CMS_MSG_ERR);
331 void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base,
338 	nlm_write_cms_reg(base, CMS_TRACE_BASE_ADDR, trace_base);
339 	nlm_write_cms_reg(base, CMS_TRACE_LIMIT_ADDR, trace_limit);
341 	val = nlm_read_cms_reg(base, CMS_TRACE_CONFIG);
348 	nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
351 void nlm_cms_endian_byte_swap (uint64_t base, int en)
353 	nlm_write_cms_reg(base, CMS_MSG_ENDIAN_SWAP, en);