Lines Matching refs:LGE_MODE1
379 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
417 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
420 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
1283 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1290 CSR_WRITE_4(sc, LGE_MODE1,
1293 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1300 CSR_WRITE_4(sc, LGE_MODE1,
1303 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1313 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1320 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1326 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1459 CSR_WRITE_4(sc, LGE_MODE1,
1465 CSR_WRITE_4(sc, LGE_MODE1,
1538 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);