Lines Matching refs:this_controller
187 SCIC_SDS_CONTROLLER_T *this_controller;
188 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
190 this_controller->phy_startup_timer_pending = FALSE;
196 status = scic_sds_controller_start_next_phy(this_controller);
203 * @param this_controller
207 SCIC_SDS_CONTROLLER_T *this_controller
210 this_controller->phy_startup_timer = scic_cb_timer_create(
211 this_controller,
213 this_controller
216 if (this_controller->phy_startup_timer == NULL)
222 this_controller->next_phy_to_start = 0;
223 this_controller->phy_startup_timer_pending = FALSE;
233 * @param this_controller
236 SCIC_SDS_CONTROLLER_T *this_controller
239 this_controller->power_control.timer = scic_cb_timer_create(
240 this_controller,
242 this_controller
246 this_controller->power_control.requesters,
248 sizeof(this_controller->power_control.requesters)
251 this_controller->power_control.phys_waiting = 0;
252 this_controller->power_control.remote_devices_granted_power = 0;
269 * @param[in] this_controller This parameter specifies the controller
275 SCIC_SDS_CONTROLLER_T *this_controller
279 &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
281 (sizeof(U32) * this_controller->completion_queue_entries),
286 &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
288 this_controller->remote_node_entries * sizeof(SCU_REMOTE_NODE_CONTEXT_T),
293 &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
295 this_controller->task_context_entries * sizeof(SCU_TASK_CONTEXT_T),
303 &this_controller->uf_control
307 &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
309 scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
318 * @param[in] this_controller
323 SCIC_SDS_CONTROLLER_T *this_controller
329 &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
331 (sizeof(U32) * this_controller->completion_queue_entries),
339 &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
341 this_controller->remote_node_entries * sizeof(SCU_REMOTE_NODE_CONTEXT_T),
349 &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
351 this_controller->task_context_entries * sizeof(SCU_TASK_CONTEXT_T),
359 &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
361 scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
375 * @param[in] this_controller
380 SCIC_SDS_CONTROLLER_T *this_controller
387 mde = &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE];
388 this_controller->completion_queue = (U32*) mde->virtual_address;
389 SMU_CQBAR_WRITE(this_controller, mde->physical_address);
393 mde = &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT];
394 this_controller->remote_node_context_table = (SCU_REMOTE_NODE_CONTEXT_T *)
396 SMU_RNCBAR_WRITE(this_controller, mde->physical_address);
399 mde = &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT];
400 this_controller->task_context_table = (SCU_TASK_CONTEXT_T *)
402 SMU_HTTBAR_WRITE(this_controller, mde->physical_address);
404 mde = &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER];
406 &this_controller->uf_control, mde, this_controller
412 this_controller,
413 this_controller->uf_control.headers.physical_address);
415 this_controller,
416 this_controller->uf_control.address_table.physical_address);
420 this_controller,
425 this_controller,
434 * @param[in] this_controller
439 SCIC_SDS_CONTROLLER_T *this_controller
446 task_assignment = SMU_TCA_READ(this_controller, 0);
452 | (SMU_TCA_GEN_VAL(ENDING, this_controller->task_context_entries - 1))
456 SMU_TCA_WRITE(this_controller, 0, task_assignment);
462 * @param[in] this_controller
465 SCIC_SDS_CONTROLLER_T *this_controller
473 this_controller->completion_queue_get = 0;
476 SMU_CQC_QUEUE_LIMIT_SET(this_controller->completion_queue_entries - 1)
477 | SMU_CQC_EVENT_LIMIT_SET(this_controller->completion_event_entries - 1)
480 SMU_CQC_WRITE(this_controller, completion_queue_control_value);
490 SMU_CQGR_WRITE(this_controller, completion_queue_get_value);
492 this_controller->completion_queue_get = completion_queue_get_value;
500 SMU_CQPR_WRITE(this_controller, completion_queue_put_value);
503 for (index = 0; index < this_controller->completion_queue_entries; index++)
508 this_controller->completion_queue[index] = 0x80000000;
515 * @param[in] this_controller
518 SCIC_SDS_CONTROLLER_T *this_controller
527 SCU_UFQC_GEN_VAL(QUEUE_SIZE, this_controller->uf_control.address_table.count);
529 SCU_UFQC_WRITE(this_controller, frame_queue_control_value);
537 SCU_UFQGP_WRITE(this_controller, frame_queue_get_value);
542 SCU_UFQPP_WRITE(this_controller, frame_queue_put_value);
548 * @param[in] this_controller
551 SCIC_SDS_CONTROLLER_T *this_controller
556 port_task_scheduler_value = SCU_PTSGCR_READ(this_controller);
561 SCU_PTSGCR_WRITE(this_controller, port_task_scheduler_value);
571 * @param this_controller
574 SCIC_SDS_CONTROLLER_T *this_controller
581 this_controller, this_controller->lex_registers + 0xC4);
584 sci_base_object_get_logger(this_controller),
587 this_controller, lex_status
594 * @param this_controller
597 SCIC_SDS_CONTROLLER_T *this_controller
602 this_controller, this_controller->lex_registers + 0x28, 0x0020FFFF) ;
606 this_controller, this_controller->lex_registers + 0xC0, 0x00000700);
608 scic_sds_controller_lex_status_read_fence(this_controller);
612 this_controller, this_controller->lex_registers + 0x70, 0x00000002);
616 this_controller, this_controller->lex_registers + 0xC0, 0x00000300);
618 scic_sds_controller_lex_status_read_fence(this_controller);
622 this_controller, this_controller->lex_registers + 0x28, 0x0000FFFF);
625 scic_sds_controller_afe_initialization(this_controller);
627 scic_sds_controller_lex_status_read_fence(this_controller);
632 this_controller, this_controller->lex_registers + 0x28, 0x0000FFFF);
637 this_controller, this_controller->lex_registers + 0x28, 0x0040FFFF) ;
640 scic_sds_controller_afe_initialization(this_controller);
642 scic_sds_controller_lex_status_read_fence(this_controller);
647 this_controller, this_controller->lex_registers + 0x28, 0x0040FFFF) ;
652 this_controller, this_controller->lex_registers + 0xC0, 0x00000100);
654 scic_sds_controller_lex_status_read_fence(this_controller);
658 this_controller, this_controller->lex_registers + 0xC0, 0x00000000);
660 scic_sds_controller_lex_status_read_fence(this_controller);
665 this_controller, this_controller->lex_registers + 0xC0, 0x00000800);
667 scic_sds_controller_lex_status_read_fence(this_controller);
674 this_controller, this_controller->lex_registers + 0xC0, 0x27800000);
679 this_controller, this_controller->lex_registers + 0x28, 0x0000FF77);
682 this_controller, this_controller->lex_registers + 0x28, 0x0000FF55);
685 this_controller, this_controller->lex_registers + 0x28, 0x0000FF11);
688 this_controller, this_controller->lex_registers + 0x28, 0x0000FF00);
691 this_controller, this_controller->lex_registers + 0x28, 0x0003FF00);
701 * @param[in] this_controller
704 SCIC_SDS_CONTROLLER_T *this_controller
708 this_controller, this_controller->lex_registers + 0x88, 0x09090909);
711 this_controller, this_controller->lex_registers + 0x8C, 0xcac9c862);
726 * @param[in] this_controller
732 SCIC_SDS_CONTROLLER_T *this_controller
746 this_controller, afe_pll_control, 0x00247506);
750 this_controller, afe_dfx_transceiver_status_clear, 0x00000000);
762 this_controller, afe_transceiver_control0[0], 0x0700141e);
766 scu_afe_register_write(this_controller, afe_pll_control, 0x00200506);
767 scu_afe_register_write(this_controller, afe_pll_dfx_control, 0x10000080);
770 scu_afe_register_write(this_controller, afe_bias_control[0], 0x00124814);
771 scu_afe_register_write(this_controller, afe_bias_control[1], 0x24900000);
775 this_controller, afe_transceiver_control0[0], 0x0702941e);
778 this_controller, afe_transceiver_control1[0], 0x0000000a);
782 this_controller, afe_transceiver_equalization_control[0], 0x00ba2223);
785 this_controller, reserved_0028_003c[2], 0x00000000);
789 this_controller, afe_dfx_transmit_control_register[0], 0x03815428);
793 this_controller, afe_dfx_transceiver_status_clear, 0x00000010);
796 scu_afe_register_write(this_controller, afe_pll_control, 0x00200504);
799 scu_afe_register_write(this_controller, afe_pll_control, 0x00200505);
804 scu_afe_register_write(this_controller, afe_pll_control, 0x00200501);
806 while ((scu_afe_register_read(this_controller, afe_common_status) & 0x03) != 0x03)
817 this_controller, afe_transceiver_control0[0], 0x07028c11);
823 SCIC_SDS_CONTROLLER_T *this_controller
832 this_controller, afe_dfx_master_control0, 0x0000000f);
835 this_controller, afe_bias_control, 0x0000aa00);
838 this_controller, afe_pll_control0, 0x80000908);
845 this_controller, afe_common_block_status);
853 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000157);
856 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016d1a);
859 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01501014);
862 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00000000);
865 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0, 0x000bdd08);
867 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1, 0x000ffc00);
869 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2, 0x000b7c09);
871 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3, 0x000afc6e);
874 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00000000);
877 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x3208903f);
882 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000154);
886 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x3801611a);
890 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x3801631a);
894 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016318);
898 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016319);
902 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016319);
908 this_controller, afe_dfx_master_control0, 0x00010f00);
913 this_controller, afe_dfx_master_control0, 0x0081000f);
916 this_controller, afe_bias_control, 0x0000aa00);
919 this_controller, afe_pll_control0, 0x80000908);
928 this_controller, afe_common_block_status);
934 this_controller, afe_dfx_master_control1, 0x00000000);
937 this_controller, afe_pmsn_master_control0, 0x7bd316ad);
943 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000174);
946 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00030000);
949 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0000651a);
952 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006518);
955 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006518);
960 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00000000);
963 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0, 0x000bdd08);
965 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1, 0x000ffc00);
967 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2, 0x000b7c09);
969 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3, 0x000afc6e);
974 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000154);
979 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x00000080);
982 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x01041042);
985 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x320891bf);
989 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006118);
993 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006108);
998 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x0317108f);
1002 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01e00021);
1006 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006109);
1010 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006009);
1014 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006209);
1020 this_controller, afe_dfx_master_control0, 0x00010f00);
1027 SCIC_SDS_CONTROLLER_T *this_controller
1035 (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_A0)
1036 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_A2)
1037 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_B0)
1038 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_C0)
1039 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_C1)
1046 this_controller->pci_revision = SCIC_SDS_PCI_REVISION_C1;
1050 this_controller->oem_parameters.sds1.controller.cable_selection_mask;
1055 this_controller, afe_dfx_master_control0, 0x0081000f);
1059 (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1060 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1061 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1066 this_controller, afe_pmsn_master_control2, 0x0007FFFF);
1071 if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1072 scu_afe_register_write(this_controller, afe_bias_control, 0x00005500);
1073 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1074 scu_afe_register_write(this_controller, afe_bias_control, 0x00005A00);
1075 else if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1076 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0) )
1077 scu_afe_register_write(this_controller, afe_bias_control, 0x00005F00);
1078 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1079 scu_afe_register_write(this_controller, afe_bias_control, 0x00005500);
1085 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1086 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1088 scu_afe_register_write(this_controller, afe_pll_control0, 0x80040908);
1090 else if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1091 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0) )
1093 scu_afe_register_write(this_controller, afe_pll_control0, 0x80040A08);
1095 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1097 scu_afe_register_write(this_controller, afe_pll_control0, 0x80000b08);
1099 scu_afe_register_write(this_controller, afe_pll_control0, 0x00000b08);
1101 scu_afe_register_write(this_controller, afe_pll_control0, 0x80000b08);
1112 this_controller, afe_common_block_status);
1117 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1118 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1122 this_controller, afe_pmsn_master_control0, 0x7bcc96ad);
1131 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1132 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1137 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00004512
1142 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x0050100F
1146 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1150 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00030000
1154 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1158 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00010202
1165 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00014500
1169 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1173 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00010202
1180 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0001C500
1186 if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1189 this_controller,
1194 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1197 this_controller,
1202 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1206 this_controller,
1216 this_controller,
1221 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1224 this_controller,
1234 this_controller,
1239 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1242 this_controller,
1253 this_controller,
1262 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1263 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1267 this_controller,
1274 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1275 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1276 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0) )
1281 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00004100);
1284 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1287 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00014100);
1290 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1293 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0001c100);
1298 if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1301 this_controller,
1306 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1309 this_controller,
1314 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1317 this_controller,
1325 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000);
1327 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1330 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01400c0f);
1334 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x3f6f103f);
1339 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000);
1341 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1344 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1,
1351 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x000003e0);
1355 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0,
1363 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000);
1369 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0,
1370 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control0
1375 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1,
1376 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control1
1381 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2,
1382 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control2
1387 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3,
1388 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control3
1395 this_controller, afe_dfx_master_control0, 0x00010f00);
1412 * @param[in,out] this_controller This parameter indicates the controller
1421 SCIC_SDS_CONTROLLER_T *this_controller,
1426 sci_base_object_get_logger(this_controller),
1429 this_controller, status
1432 if (this_controller->parent.state_machine.current_state_id
1438 scic_sds_controller_get_base_state_machine(this_controller),
1442 scic_cb_controller_start_complete(this_controller, status);
1461 SCIC_SDS_CONTROLLER_T *this_controller;
1462 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
1465 scic_sds_controller_get_base_state_machine(this_controller)
1471 this_controller, SCI_FAILURE_TIMEOUT
1477 scic_sds_controller_get_base_state_machine(this_controller),
1487 sci_base_object_get_logger(this_controller),
1497 * @param[in] this_controller
1502 SCIC_SDS_CONTROLLER_T *this_controller
1511 for (index = 0; index < this_controller->logical_port_entries; index++)
1513 port_status = this_controller->port_table[index].
1514 state_handlers->parent.stop_handler(&this_controller->port_table[index].parent);
1523 sci_base_object_get_logger(this_controller),
1526 this_controller->port_table[index].logical_port_index, port_status
1537 * @param[in] this_controller
1541 SCIC_SDS_CONTROLLER_T *this_controller
1545 this_controller,
1546 this_controller->phy_startup_timer,
1550 this_controller->phy_startup_timer_pending = TRUE;
1556 * @param[in] this_controller
1559 SCIC_SDS_CONTROLLER_T *this_controller
1563 this_controller,
1564 this_controller->phy_startup_timer
1567 this_controller->phy_startup_timer_pending = FALSE;
1578 * @param[in] this_controller This parameter specifies the controller
1584 SCIC_SDS_CONTROLLER_T *this_controller
1591 SCIC_SDS_PHY_T *the_phy = & this_controller->phy_table[index];
1595 this_controller->oem_parameters.sds1.controller.mode_type
1600 this_controller->oem_parameters.sds1.controller.mode_type
1632 this_controller->port_agent.phy_ready_mask
1633 != this_controller->port_agent.phy_configured_mask
1652 * @param[in] this_controller This parameter specifies the controller
1658 SCIC_SDS_CONTROLLER_T *this_controller
1665 if (this_controller->phy_startup_timer_pending == FALSE)
1667 if (this_controller->next_phy_to_start == SCI_MAX_PHYS)
1671 if (scic_sds_controller_is_start_complete(this_controller) == TRUE)
1674 this_controller, SCI_SUCCESS
1682 the_phy = &this_controller->phy_table[this_controller->next_phy_to_start];
1685 this_controller->oem_parameters.sds1.controller.mode_type
1691 this_controller->next_phy_to_start++;
1698 return scic_sds_controller_start_next_phy(this_controller);
1706 scic_sds_controller_phy_timer_start(this_controller);
1711 sci_base_object_get_logger(this_controller),
1714 this_controller->phy_table[this_controller->next_phy_to_start].phy_index,
1719 this_controller->next_phy_to_start++;
1729 * @param[in] this_controller
1734 SCIC_SDS_CONTROLLER_T *this_controller
1745 phy_status = scic_phy_stop(&this_controller->phy_table[index]);
1755 sci_base_object_get_logger(this_controller),
1758 this_controller->phy_table[index].phy_index, phy_status
1769 * @param[in] this_controller
1774 SCIC_SDS_CONTROLLER_T *this_controller
1783 for (index = 0; index < this_controller->remote_node_entries; index++)
1785 if (this_controller->device_table[index] != SCI_INVALID_HANDLE)
1788 device_status = scic_remote_device_stop(this_controller->device_table[index], 0);
1796 sci_base_object_get_logger(this_controller),
1799 this_controller->device_table[index], device_status
1815 * @param this_controller
1819 SCIC_SDS_CONTROLLER_T *this_controller
1823 this_controller, this_controller->power_control.timer,
1827 this_controller->power_control.timer_started = TRUE;
1833 * @param this_controller
1837 SCIC_SDS_CONTROLLER_T *this_controller
1840 if (this_controller->power_control.timer_started)
1843 this_controller, this_controller->power_control.timer
1846 this_controller->power_control.timer_started = FALSE;
1853 * @param this_controller
1857 SCIC_SDS_CONTROLLER_T *this_controller
1860 scic_sds_controller_power_control_timer_stop(this_controller);
1861 scic_sds_controller_power_control_timer_start(this_controller);
1874 SCIC_SDS_CONTROLLER_T *this_controller;
1875 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
1877 this_controller->power_control.remote_devices_granted_power = 0;
1879 if (this_controller->power_control.phys_waiting == 0)
1881 this_controller->power_control.timer_started = FALSE;
1890 && (this_controller->power_control.phys_waiting != 0);
1893 if (this_controller->power_control.requesters[i] != NULL)
1895 if ( this_controller->power_control.remote_devices_granted_power <
1896 this_controller->oem_parameters.sds1.controller.max_number_concurrent_device_spin_up
1899 the_phy = this_controller->power_control.requesters[i];
1900 this_controller->power_control.requesters[i] = NULL;
1901 this_controller->power_control.phys_waiting--;
1902 this_controller->power_control.remote_devices_granted_power ++;
1912 current_requester_phy = this_controller->power_control.requesters[j];
1923 this_controller->power_control.requesters[j] = NULL;
1924 this_controller->power_control.phys_waiting--;
1939 scic_sds_controller_power_control_timer_start(this_controller);
1946 * @param[in] this_controller
1950 SCIC_SDS_CONTROLLER_T *this_controller,
1956 if( this_controller->power_control.remote_devices_granted_power <
1957 this_controller->oem_parameters.sds1.controller.max_number_concurrent_device_spin_up
1960 this_controller->power_control.remote_devices_granted_power ++;
1965 scic_sds_controller_power_control_timer_restart (this_controller);
1975 current_phy = &this_controller->phy_table[i];
1992 this_controller->power_control.requesters[the_phy->phy_index] = the_phy;
1993 this_controller->power_control.phys_waiting++;
2002 * @param[in] this_controller
2006 SCIC_SDS_CONTROLLER_T *this_controller,
2012 if (this_controller->power_control.requesters[the_phy->phy_index] != NULL)
2014 this_controller->power_control.phys_waiting--;
2017 this_controller->power_control.requesters[the_phy->phy_index] = NULL;
2028 * @param[in] this_controller
2036 SCIC_SDS_CONTROLLER_T *this_controller
2039 U32 get_value = this_controller->completion_queue_get;
2043 == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
2058 * @param[in] this_controller
2065 SCIC_SDS_CONTROLLER_T *this_controller,
2073 io_request = this_controller->io_request_table[index];
2081 == this_controller->io_request_sequence[index]
2094 * @param[in] this_controller
2101 SCIC_SDS_CONTROLLER_T *this_controller,
2115 io_request = this_controller->io_request_table[index];
2117 sci_base_object_get_logger(this_controller),
2132 device = this_controller->device_table[index];
2134 sci_base_object_get_logger(this_controller),
2148 sci_base_object_get_logger(this_controller),
2159 scic_sds_controller_get_base_state_machine(this_controller),
2168 * @param[in] this_controller
2175 SCIC_SDS_CONTROLLER_T *this_controller,
2191 = this_controller->uf_control.buffers.array[frame_index].header;
2192 this_controller->uf_control.buffers.array[frame_index].state
2200 scic_sds_controller_release_frame(this_controller, frame_index);
2207 phy = &this_controller->phy_table[index];
2224 phy = &this_controller->phy_table[index];
2229 if (index < this_controller->remote_node_entries)
2230 device = this_controller->device_table[index];
2237 scic_sds_controller_release_frame(this_controller, frame_index);
2252 * @param[in] this_controller
2259 SCIC_SDS_CONTROLLER_T *this_controller,
2275 sci_base_object_get_logger(this_controller),
2278 this_controller, completion_entry
2284 this_controller->parent.error = SCI_CONTROLLER_FATAL_MEMORY_ERROR;
2287 scic_sds_controller_get_base_state_machine(this_controller),
2295 sci_base_object_get_logger(this_controller),
2298 this_controller, completion_entry
2303 io_request = this_controller->io_request_table[index];
2312 io_request = this_controller->io_request_table[index];
2320 sci_base_object_get_logger(this_controller),
2326 this_controller, completion_entry
2332 device = this_controller->device_table[index];
2340 sci_base_object_get_logger(this_controller),
2346 this_controller, completion_entry
2361 phy = &this_controller->phy_table[index];
2368 if (index < this_controller->remote_node_entries)
2370 device = this_controller->device_table[index];
2380 sci_base_object_get_logger(this_controller),
2386 this_controller, completion_entry, index
2393 sci_base_object_get_logger(this_controller),
2406 * @param[in] this_controller
2412 SCIC_SDS_CONTROLLER_T *this_controller
2423 sci_base_object_get_logger(this_controller),
2426 this_controller
2430 sci_base_object_get_logger(this_controller),
2433 this_controller->completion_queue_get
2437 get_index = NORMALIZE_GET_POINTER(this_controller->completion_queue_get);
2438 get_cycle = SMU_CQGR_CYCLE_BIT & this_controller->completion_queue_get;
2440 event_index = NORMALIZE_EVENT_POINTER(this_controller->completion_queue_get);
2441 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & this_controller->completion_queue_get;
2445 == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
2450 completion_entry = this_controller->completion_queue[get_index];
2451 INCREMENT_COMPLETION_QUEUE_GET(this_controller, get_index, get_cycle);
2454 sci_base_object_get_logger(this_controller),
2463 scic_sds_controller_task_completion(this_controller, completion_entry);
2467 scic_sds_controller_sdma_completion(this_controller, completion_entry);
2471 scic_sds_controller_unsolicited_frame(this_controller, completion_entry);
2475 scic_sds_controller_event_completion(this_controller, completion_entry);
2481 INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
2482 scic_sds_controller_event_completion(this_controller, completion_entry);
2487 sci_base_object_get_logger(this_controller),
2499 this_controller->completion_queue_get =
2505 SMU_CQGR_WRITE(this_controller, this_controller->completion_queue_get);
2509 sci_base_object_get_logger(this_controller),
2512 this_controller->completion_queue_get
2521 * @param[in] this_controller
2527 SCIC_SDS_CONTROLLER_T * this_controller
2538 sci_base_object_get_logger(this_controller),
2541 this_controller
2545 sci_base_object_get_logger(this_controller),
2548 this_controller->completion_queue_get
2552 get_index = NORMALIZE_GET_POINTER(this_controller->completion_queue_get);
2553 get_cycle = SMU_CQGR_CYCLE_BIT & this_controller->completion_queue_get;
2555 event_index = NORMALIZE_EVENT_POINTER(this_controller->completion_queue_get);
2556 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & this_controller->completion_queue_get;
2561 this_controller->completion_queue[get_index])
2566 completion_entry = this_controller->completion_queue[get_index];
2567 INCREMENT_COMPLETION_QUEUE_GET(this_controller, get_index, get_cycle);
2570 sci_base_object_get_logger(this_controller),
2579 scic_sds_controller_task_completion(this_controller, completion_entry);
2583 INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
2591 sci_base_object_get_logger(this_controller),
2603 this_controller->completion_queue_get =
2609 SMU_CQGR_WRITE(this_controller, this_controller->completion_queue_get);
2613 sci_base_object_get_logger(this_controller),
2616 this_controller->completion_queue_get
2638 SCIC_SDS_CONTROLLER_T *this_controller,
2645 sci_base_object_get_logger(this_controller),
2648 this_controller, interrupt_status
2655 && (!scic_sds_controller_completion_queue_has_entries(this_controller))
2665 this_controller->encountered_fatal_error = TRUE;
2668 if (scic_sds_controller_completion_queue_has_entries(this_controller))
2692 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
2708 interrupt_status = SMU_ISR_READ(this_controller);
2735 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2744 if (this_controller->encountered_fatal_error == TRUE)
2747 sci_base_object_get_logger(this_controller),
2753 scic_sds_controller_get_base_state_machine(this_controller),
2757 else if (scic_sds_controller_completion_queue_has_entries(this_controller))
2759 if (this_controller->restrict_completions == FALSE)
2760 scic_sds_controller_process_completions(this_controller);
2762 scic_sds_controller_transitioned_process_completions(this_controller);
2775 this_controller,
2798 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
2800 interrupt_status = SMU_ISR_READ(this_controller);
2802 this_controller, interrupt_status
2824 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2835 SMU_IMR_WRITE(this_controller, 0x00000000);
2882 SCIC_SDS_CONTROLLER_T *this_controller;
2883 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2889 SMU_IMR_WRITE(this_controller, 0xFFFFFFFF);
2891 interrupt_status = SMU_ISR_READ(this_controller);
2896 && scic_sds_controller_completion_queue_has_entries(this_controller)
2901 SMU_ISR_WRITE(this_controller, SMU_ISR_COMPLETION);
2916 SMU_ISR_WRITE(this_controller, 0x00000000);
2917 SMU_IMR_WRITE(this_controller, 0x00000000);
2934 SCIC_SDS_CONTROLLER_T *this_controller;
2935 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2944 interrupt_status = SMU_ISR_READ(this_controller);
2950 sci_base_object_get_logger(this_controller),
2958 scic_sds_controller_get_base_state_machine(this_controller),
2966 && !scic_sds_controller_completion_queue_has_entries(this_controller)
2970 sci_base_object_get_logger(this_controller),
2978 scic_sds_controller_get_base_state_machine(this_controller),
2984 if (scic_sds_controller_completion_queue_has_entries(this_controller))
2986 scic_sds_controller_process_completions(this_controller);
2991 this_controller,
2996 SMU_IMR_WRITE(this_controller, 0x00000000);
3014 SCIC_SDS_CONTROLLER_T *this_controller;
3015 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3017 if (scic_sds_controller_completion_queue_has_entries(this_controller))
3025 SMU_ISR_WRITE(this_controller, SMU_ISR_COMPLETION);
3031 SMU_IMR_WRITE(this_controller, 0xFF000000);
3032 SMU_IMR_WRITE(this_controller, 0x00000000);
3049 SCIC_SDS_CONTROLLER_T *this_controller;
3050 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3060 if (scic_sds_controller_completion_queue_has_entries(this_controller))
3062 scic_sds_controller_process_completions(this_controller);
3066 SMU_ISR_WRITE(this_controller, SMU_ISR_COMPLETION);
3068 SMU_IMR_WRITE(this_controller, 0xFF000000);
3069 SMU_IMR_WRITE(this_controller, 0x00000000);
3089 SCIC_SDS_CONTROLLER_T *this_controller;
3090 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3093 interrupt_status = SMU_ISR_READ(this_controller);
3108 SMU_IMR_WRITE(this_controller, 0x000000FF);
3109 SMU_IMR_WRITE(this_controller, 0x00000000);
3126 SCIC_SDS_CONTROLLER_T *this_controller;
3127 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3136 interrupt_status = SMU_ISR_READ(this_controller);
3140 && scic_sds_controller_completion_queue_has_entries(this_controller)
3143 scic_sds_controller_process_completions(this_controller);
3145 SMU_ISR_WRITE(this_controller, SMU_ISR_QUEUE_SUSPEND);
3150 sci_base_object_get_logger(this_controller),
3157 scic_sds_controller_get_base_state_machine(this_controller),
3166 SMU_IMR_WRITE(this_controller, 0x00000000);
3218 * @param[in] this_controller
3225 SCIC_SDS_CONTROLLER_T *this_controller,
3230 if (this_controller->state_handlers->link_up_handler != NULL)
3232 this_controller->state_handlers->link_up_handler(
3233 this_controller, the_port, the_phy);
3238 sci_base_object_get_logger(this_controller),
3243 scic_sds_controller_get_base_state_machine(this_controller))
3251 * @param[in] this_controller
3256 SCIC_SDS_CONTROLLER_T *this_controller,
3261 if (this_controller->state_handlers->link_down_handler != NULL)
3263 this_controller->state_handlers->link_down_handler(
3264 this_controller, the_port, the_phy);
3269 sci_base_object_get_logger(this_controller),
3274 scic_sds_controller_get_base_state_machine(this_controller))
3283 * @param[in] this_controller
3287 SCIC_SDS_CONTROLLER_T * this_controller,
3291 if (this_controller->state_handlers->remote_device_started_handler != NULL)
3293 this_controller->state_handlers->remote_device_started_handler(
3294 this_controller, the_device
3300 sci_base_object_get_logger(this_controller),
3303 this_controller,
3306 scic_sds_controller_get_base_state_machine(this_controller))
3315 * @param[in] this_controller
3318 SCIC_SDS_CONTROLLER_T * this_controller
3323 for (index = 0; index < this_controller->remote_node_entries; index++)
3326 (this_controller->device_table[index] != NULL)
3328 this_controller->device_table[index]->parent.state_machine.current_state_id
3344 * @param[in] this_controller
3348 SCIC_SDS_CONTROLLER_T * this_controller,
3352 if (this_controller->state_handlers->remote_device_stopped_handler != NULL)
3354 this_controller->state_handlers->remote_device_stopped_handler(
3355 this_controller, the_device
3361 sci_base_object_get_logger(this_controller),
3364 this_controller,
3367 scic_sds_controller_get_base_state_machine(this_controller))
3376 * @param[in] this_controller
3380 SCIC_SDS_CONTROLLER_T *this_controller,
3385 sci_base_object_get_logger(this_controller),
3388 this_controller, request
3391 SMU_PCP_WRITE(this_controller, request);
3403 * @param[in] this_controller This parameter specifies the controller for
3411 SCIC_SDS_CONTROLLER_T *this_controller,
3418 this_controller, this_request->io_tag
3436 * @param[in] this_controller
3442 SCIC_SDS_CONTROLLER_T * this_controller,
3448 if (task_index < this_controller->task_context_entries)
3450 return &this_controller->task_context_table[task_index];
3459 * @param[in] this_controller
3465 SCIC_SDS_CONTROLLER_T *this_controller,
3475 * @param[in] this_controller
3482 SCIC_SDS_CONTROLLER_T *this_controller,
3491 if (task_index < this_controller->task_context_entries)
3493 if (this_controller->io_request_table[task_index] != SCI_INVALID_HANDLE)
3497 if (task_sequence == this_controller->io_request_sequence[task_index])
3499 return this_controller->io_request_table[task_index];
3512 * @param[in] this_controller This is the controller object which contains
3524 SCIC_SDS_CONTROLLER_T * this_controller,
3533 &this_controller->available_remote_nodes, remote_node_count
3538 this_controller->device_table[node_index] = the_device;
3553 * @param[in] this_controller
3560 SCIC_SDS_CONTROLLER_T * this_controller,
3567 if (this_controller->device_table[node_id] == the_device)
3569 this_controller->device_table[node_id] = SCI_INVALID_HANDLE;
3572 &this_controller->available_remote_nodes, remote_node_count, node_id
3581 * @param[in] this_controller
3587 SCIC_SDS_CONTROLLER_T *this_controller,
3592 (node_id < this_controller->remote_node_entries)
3593 && (this_controller->device_table[node_id] != SCI_INVALID_HANDLE)
3596 return &this_controller->remote_node_context_table[node_id];
3639 * @param[in] this_controller
3645 SCIC_SDS_CONTROLLER_T *this_controller,
3650 &this_controller->uf_control, frame_index) == TRUE)
3651 SCU_UFQGP_WRITE(this_controller, this_controller->uf_control.get);
3656 SCIC_SDS_CONTROLLER_T *this_controller
3660 &this_controller->parent.state_machine_logger,
3661 &this_controller->parent.state_machine,
3662 &this_controller->parent.parent,
3670 SCIC_SDS_CONTROLLER_T *this_controller
3674 &this_controller->parent.state_machine_logger,
3675 &this_controller->parent.state_machine
3694 SCIC_SDS_CONTROLLER_T *this_controller
3700 this_controller->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
3703 this_controller->oem_parameters.sds1.controller.max_number_concurrent_device_spin_up = 1;
3706 this_controller->oem_parameters.sds1.controller.ssc_sata_tx_spread_level = 0;
3707 this_controller->oem_parameters.sds1.controller.ssc_sas_tx_spread_level = 0;
3708 this_controller->oem_parameters.sds1.controller.ssc_sas_tx_type = 0;
3711 this_controller->oem_parameters.sds1.controller.cable_selection_mask = 0;
3716 this_controller->oem_parameters.sds1.ports[index].phy_mask = 0;
3724 this_controller->user_parameters.sds1.phys[index].max_speed_generation = 2;
3727 this_controller->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
3728 this_controller->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
3729 this_controller->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
3735 this_controller->oem_parameters.sds1.phys[index].sas_address.sci_format.high
3739 this_controller->oem_parameters.sds1.phys[index].sas_address.sci_format.low
3740 = 0x00000001 + this_controller->controller_index;
3742 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
3743 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
3744 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0) )
3746 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control0 = 0x000E7C03;
3747 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control1 = 0x000E7C03;
3748 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control2 = 0x000E7C03;
3749 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control3 = 0x000E7C03;
3753 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control0 = 0x000BDD08;
3754 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control1 = 0x000B7069;
3755 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control2 = 0x000B7C09;
3756 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control3 = 0x000AFC6E;
3760 this_controller->user_parameters.sds1.stp_inactivity_timeout = 5;
3761 this_controller->user_parameters.sds1.ssp_inactivity_timeout = 5;
3762 this_controller->user_parameters.sds1.stp_max_occupancy_timeout = 5;
3763 this_controller->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
3764 this_controller->user_parameters.sds1.no_outbound_task_timeout = 20;
3772 * @param[in] this_controller This parameter specifies the core
3783 SCIC_SDS_CONTROLLER_T * this_controller
3791 sci_base_object_get_logger(this_controller),
3794 this_controller
3797 if(this_controller->phy_startup_timer != NULL)
3799 scic_cb_timer_destroy(this_controller, this_controller->phy_startup_timer);
3800 this_controller->phy_startup_timer = NULL;
3803 if(this_controller->power_control.timer != NULL)
3805 scic_cb_timer_destroy(this_controller, this_controller->power_control.timer);
3806 this_controller->power_control.timer = NULL;
3809 if(this_controller->timeout_timer != NULL)
3811 scic_cb_timer_destroy(this_controller, this_controller->timeout_timer);
3812 this_controller->timeout_timer = NULL;
3816 this_controller,
3817 &this_controller->port_agent);
3821 port = &this_controller->port_table[index];
3822 scic_sds_port_release_resource(this_controller, port);
3827 phy = &this_controller->phy_table[index];
3828 scic_sds_phy_release_resource(this_controller, phy);
3839 * @param[in] this_controller This parameter specifies the core
3845 SCIC_SDS_CONTROLLER_T * this_controller
3850 this_controller, SCI_SUCCESS
3866 SCIC_SDS_CONTROLLER_T *this_controller;
3869 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3879 memset(this_controller, 0, sizeof(SCIC_SDS_CONTROLLER_T));
3885 this_controller->controller_index =
3886 scic_sds_library_get_controller_index(my_library, this_controller);
3888 this_controller->pci_revision = my_library->pci_revision;
3891 &this_controller->parent,
3894 this_controller->memory_descriptors,
3895 ARRAY_SIZE(this_controller->memory_descriptors),
3901 scic_sds_controller_initialize_state_logging(this_controller);
3903 scic_sds_pci_bar_initialization(this_controller);
3915 SCIC_SDS_CONTROLLER_T *this_controller;
3916 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3925 if (this_controller->state_handlers->parent.initialize_handler != NULL)
3927 status = this_controller->state_handlers->parent.initialize_handler(
3934 sci_base_object_get_logger(this_controller),
3938 scic_sds_controller_get_base_state_machine(this_controller))
3981 SCIC_SDS_CONTROLLER_T *this_controller;
3982 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3991 if (this_controller->state_handlers->parent.start_handler != NULL)
3993 status = this_controller->state_handlers->parent.start_handler(
4000 sci_base_object_get_logger(this_controller),
4004 scic_sds_controller_get_base_state_machine(this_controller))
4019 SCIC_SDS_CONTROLLER_T *this_controller;
4020 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4029 if (this_controller->state_handlers->parent.stop_handler != NULL)
4031 status = this_controller->state_handlers->parent.stop_handler(
4038 sci_base_object_get_logger(this_controller),
4042 scic_sds_controller_get_base_state_machine(this_controller))
4056 SCIC_SDS_CONTROLLER_T *this_controller;
4057 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4066 if (this_controller->state_handlers->parent.reset_handler != NULL)
4068 status = this_controller->state_handlers->parent.reset_handler(
4075 sci_base_object_get_logger(this_controller),
4079 scic_sds_controller_get_base_state_machine(this_controller))
4169 SCIC_SDS_CONTROLLER_T *this_controller;
4170 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4179 status = this_controller->state_handlers->parent.start_io_handler(
4180 &this_controller->parent,
4198 SCIC_SDS_CONTROLLER_T *this_controller;
4199 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4208 status = this_controller->state_handlers->terminate_request_handler(
4209 &this_controller->parent,
4226 SCIC_SDS_CONTROLLER_T *this_controller;
4227 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4236 status = this_controller->state_handlers->parent.complete_io_handler(
4237 &this_controller->parent,
4257 SCIC_SDS_CONTROLLER_T *this_controller;
4258 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4267 if (this_controller->state_handlers->parent.start_task_handler != NULL)
4269 status = this_controller->state_handlers->parent.start_task_handler(
4270 &this_controller->parent,
4297 SCIC_SDS_CONTROLLER_T *this_controller;
4298 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4307 if (this_controller->state_handlers->parent.complete_task_handler != NULL)
4309 status = this_controller->state_handlers->parent.complete_task_handler(
4310 &this_controller->parent,
4337 SCIC_SDS_CONTROLLER_T *this_controller;
4338 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4347 if (port_index < this_controller->logical_port_entries)
4349 *port_handle = &this_controller->port_table[port_index];
4365 SCIC_SDS_CONTROLLER_T *this_controller;
4366 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4375 if (phy_index < ARRAY_SIZE(this_controller->phy_table))
4377 *phy_handle = &this_controller->phy_table[phy_index];
4383 sci_base_object_get_logger(this_controller),
4386 this_controller, phy_index
4400 SCIC_SDS_CONTROLLER_T *this_controller;
4401 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4410 if (!sci_pool_empty(this_controller->tci_pool))
4412 sci_pool_get(this_controller->tci_pool, task_context);
4414 sequence_count = this_controller->io_request_sequence[task_context];
4432 SCIC_SDS_CONTROLLER_T *this_controller;
4433 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4447 if (!sci_pool_full(this_controller->tci_pool))
4449 if (sequence == this_controller->io_request_sequence[index])
4452 this_controller->io_request_sequence[index]);
4454 sci_pool_put(this_controller->tci_pool, index);
4469 SCIC_SDS_CONTROLLER_T *this_controller;
4470 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4472 ASSERT(this_controller->smu_registers != NULL);
4474 SMU_IMR_WRITE(this_controller, 0x00000000);
4483 SCIC_SDS_CONTROLLER_T *this_controller;
4484 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4486 ASSERT(this_controller->smu_registers != NULL);
4488 SMU_IMR_WRITE(this_controller, 0xffffffff);
4498 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4509 (this_controller->parent.state_machine.current_state_id
4511 || (this_controller->parent.state_machine.current_state_id
4518 this_controller->remote_node_entries =
4519 MIN(this_controller->remote_node_entries, SCI_MAX_REMOTE_DEVICES);
4520 this_controller->task_context_entries =
4521 MIN(this_controller->task_context_entries, SCU_IO_REQUEST_COUNT);
4522 this_controller->uf_control.buffers.count =
4523 MIN(this_controller->uf_control.buffers.count, SCU_UNSOLICITED_FRAME_COUNT);
4524 this_controller->completion_event_entries =
4525 MIN(this_controller->completion_event_entries, SCU_EVENT_COUNT);
4526 this_controller->completion_queue_entries =
4527 MIN(this_controller->completion_queue_entries, SCU_COMPLETION_QUEUE_COUNT);
4529 scic_sds_controller_build_memory_descriptor_table(this_controller);
4533 this_controller->remote_node_entries =
4534 MIN(this_controller->remote_node_entries, SCI_MIN_REMOTE_DEVICES);
4535 this_controller->task_context_entries =
4536 MIN(this_controller->task_context_entries, SCI_MIN_IO_REQUESTS);
4537 this_controller->uf_control.buffers.count =
4538 MIN(this_controller->uf_control.buffers.count, SCU_MIN_UNSOLICITED_FRAMES);
4539 this_controller->completion_event_entries =
4540 MIN(this_controller->completion_event_entries, SCU_MIN_EVENTS);
4541 this_controller->completion_queue_entries =
4542 MIN(this_controller->completion_queue_entries, SCU_MIN_COMPLETION_QUEUE_ENTRIES);
4544 scic_sds_controller_build_memory_descriptor_table(this_controller);
4561 * @param[in] this_controller The controller that is to be reset.
4564 SCIC_SDS_CONTROLLER_T * this_controller
4568 scic_controller_disable_interrupts(this_controller);
4571 SMU_SMUSRCR_WRITE(this_controller, 0xFFFFFFFF);
4577 SMU_CQGR_WRITE(this_controller, 0x00000000);
4580 SCU_UFQGP_WRITE(this_controller, 0x00000000);
4590 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4593 (this_controller->parent.state_machine.current_state_id
4595 || (this_controller->parent.state_machine.current_state_id
4597 || (this_controller->parent.state_machine.current_state_id
4638 (&this_controller->user_parameters), scic_parms, sizeof(*scic_parms));
4653 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4655 memcpy(scic_parms, (&this_controller->user_parameters), sizeof(*scic_parms));
4665 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4671 (this_controller->parent.state_machine.current_state_id
4673 || (this_controller->parent.state_machine.current_state_id
4675 || (this_controller->parent.state_machine.current_state_id
4687 this_controller->oem_parameters_version = scic_parms_version;
4786 (&this_controller->oem_parameters), scic_parms, sizeof(*scic_parms));
4800 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4802 memcpy(scic_parms, (&this_controller->oem_parameters), sizeof(*scic_parms));
5030 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
5045 &(this_controller->port_table[index]));
5049 SMU_CQGR_WRITE(this_controller, 0x00000000);
5050 SCU_UFQGP_WRITE(this_controller, 0x00000000);
5054 SMU_ISR_WRITE(this_controller, 0xFFFFFFFF);
5057 this_controller->completion_queue_get = 0;
5068 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
5072 scic_sds_controller_initialize_completion_queue(this_controller);
5073 scic_sds_controller_initialize_unsolicited_frame_queue(this_controller);
5075 this_controller->restrict_completions = FALSE;
5081 &(this_controller->port_table[index]));
5088 SCIC_SDS_PHY_T * curr_phy = &this_controller->phy_table[index];
5110 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
5120 if (this_controller->parent.state_machine.current_state_id
5127 if (this_controller->port_table[index].started_request_count != 0)
5136 this_controller);
5139 scic_sds_controller_ram_initialization(this_controller);
5140 this_controller->restrict_completions = restrict_completions;
5241 SCIC_SDS_CONTROLLER_T *this_controller;
5242 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5245 sci_base_object_get_logger(this_controller),
5249 scic_sds_controller_get_base_state_machine(this_controller))
5277 SCIC_SDS_CONTROLLER_T *this_controller;
5278 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5281 sci_base_object_get_logger(this_controller),
5285 scic_sds_controller_get_base_state_machine(this_controller))
5311 SCIC_SDS_CONTROLLER_T *this_controller;
5312 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5322 scic_sds_controller_release_resource(this_controller);
5327 scic_sds_controller_get_base_state_machine(this_controller),
5359 SCIC_SDS_CONTROLLER_T *this_controller;
5361 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5371 scic_sds_controller_get_base_state_machine(this_controller),
5375 this_controller->timeout_timer = scic_cb_timer_create(
5381 scic_sds_controller_initialize_power_control(this_controller);
5386 scic_sds_controller_reset_hardware(this_controller);
5389 scic_sds_controller_lex_atux_initialization(this_controller);
5393 scic_sds_controller_afe_initialization(this_controller);
5399 scic_sds_controller_afe_initialization(this_controller);
5410 SMU_SMUSRCR_WRITE(this_controller, 0x00000000);
5421 status = SMU_SMUCSR_READ(this_controller);
5431 scic_sds_controller_enable_chipwatch(this_controller);
5443 device_context_capacity = SMU_DCC_READ(this_controller);
5456 this_controller,
5457 this_controller->scu_registers->peg0.ptsg.protocol_engine[index],
5465 scic_controller_set_mode(this_controller, SCI_MODE_SPEED);
5468 this_controller->logical_port_entries =
5469 MIN(max_supported_ports, this_controller->logical_port_entries);
5471 this_controller->task_context_entries =
5472 MIN(max_supported_io_requests, this_controller->task_context_entries);
5474 this_controller->remote_node_entries =
5475 MIN(max_supported_devices, this_controller->remote_node_entries);
5484 dma_configuration = SCU_PDMACR_READ(this_controller);
5486 SCU_PDMACR_WRITE(this_controller, dma_configuration);
5489 dma_configuration = SCU_CDMACR_READ(this_controller);
5491 SCU_CDMACR_WRITE(this_controller, dma_configuration);
5504 &this_controller->phy_table[index],
5505 &this_controller->scu_registers->peg0.pe[index].tl,
5506 &this_controller->scu_registers->peg0.pe[index].ll
5514 scic_sgpio_hardware_initialize(this_controller);
5521 (index < this_controller->logical_port_entries)
5526 &this_controller->port_table[index],
5527 &this_controller->scu_registers->peg0.ptsg.port[index],
5528 &this_controller->scu_registers->peg0.ptsg.protocol_engine,
5529 &this_controller->scu_registers->peg0.viit[index]
5537 this_controller,
5538 &this_controller->port_agent
5546 scic_sds_controller_get_base_state_machine(this_controller),
5553 scic_sds_controller_release_resource(this_controller);
5604 SCIC_SDS_CONTROLLER_T * this_controller;
5606 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5609 result = scic_sds_controller_validate_memory_descriptor_table(this_controller);
5614 scic_sds_controller_ram_initialization(this_controller);
5620 sci_pool_initialize(this_controller->tci_pool);
5621 for (index = 0; index < this_controller->task_context_entries; index++)
5623 sci_pool_put(this_controller->tci_pool, index);
5628 &this_controller->available_remote_nodes,
5629 this_controller->remote_node_entries
5640 scic_sds_controller_enable_port_task_scheduler(this_controller);
5643 scic_sds_controller_assign_task_entries(this_controller);
5646 scic_sds_controller_initialize_completion_queue(this_controller);
5649 scic_sds_controller_initialize_unsolicited_frame_queue(this_controller);
5652 result = scic_sds_controller_initialize_phy_startup(this_controller);
5658 (index < this_controller->logical_port_entries) && (result == SCI_SUCCESS);
5662 result = this_controller->port_table[index].
5663 state_handlers->parent.start_handler(&this_controller->port_table[index].parent);
5668 scic_sds_controller_start_next_phy(this_controller);
5672 scic_cb_timer_start(controller, this_controller->timeout_timer, timeout);
5675 scic_sds_controller_get_base_state_machine(this_controller),
5703 SCIC_SDS_CONTROLLER_T *this_controller,
5708 scic_sds_controller_phy_timer_stop(this_controller);
5710 this_controller->port_agent.link_up_handler(
5711 this_controller, &this_controller->port_agent, port, phy
5715 scic_sds_controller_start_next_phy(this_controller);
5732 SCIC_SDS_CONTROLLER_T *this_controller,
5737 this_controller->port_agent.link_down_handler(
5738 this_controller, &this_controller->port_agent, port, phy
5767 SCIC_SDS_CONTROLLER_T *this_controller;
5768 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5772 scic_cb_timer_start(controller, this_controller->timeout_timer, timeout);
5775 scic_sds_controller_get_base_state_machine(this_controller),
5818 SCIC_SDS_CONTROLLER_T *this_controller;
5822 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5826 status = scic_sds_remote_device_start_io(this_controller, the_device, the_request);
5830 this_controller->io_request_table[
5834 this_controller,
5870 SCIC_SDS_CONTROLLER_T *this_controller;
5874 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5879 this_controller, the_device, the_request);
5884 this_controller->io_request_table[index] = SCI_INVALID_HANDLE;
5910 SCIC_SDS_CONTROLLER_T *this_controller;
5914 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5916 this_controller->io_request_table[
5920 this_controller,
5961 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)
5970 this_controller, the_device, the_request
5975 this_controller->io_request_table[
5979 this_controller,
5985 this_controller->io_request_table[
6022 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)
6034 this_controller,
6059 SCIC_SDS_CONTROLLER_T *this_controller,
6064 this_controller->port_agent.link_up_handler(
6065 this_controller, &this_controller->port_agent, port, phy
6083 SCIC_SDS_CONTROLLER_T *this_controller,
6088 this_controller->port_agent.link_down_handler(
6089 this_controller, &this_controller->port_agent, port, phy
6119 SCIC_SDS_CONTROLLER_T *this_controller;
6120 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
6185 SCIC_SDS_CONTROLLER_T *this_controller;
6186 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
6189 sci_base_object_get_logger(this_controller),
6193 scic_sds_controller_get_base_state_machine(this_controller))
6215 SCIC_SDS_CONTROLLER_T *this_controller;
6216 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
6218 if (this_controller->parent.error == SCI_CONTROLLER_FATAL_MEMORY_ERROR) {
6495 SCIC_SDS_CONTROLLER_T *this_controller;
6496 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6499 this_controller, SCI_BASE_CONTROLLER_STATE_INITIAL);
6502 &this_controller->parent.state_machine, SCI_BASE_CONTROLLER_STATE_RESET);
6521 SCIC_SDS_CONTROLLER_T *this_controller;
6522 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6525 this_controller, SCI_BASE_CONTROLLER_STATE_RESET);
6527 scic_sds_port_configuration_agent_construct(&this_controller->port_agent);
6533 &this_controller->port_table[index],
6535 this_controller
6544 &this_controller->phy_table[index],
6545 &this_controller->port_table[SCI_MAX_PORTS],
6550 this_controller->invalid_phy_mask = 0;
6553 this_controller->completion_event_entries = SCU_EVENT_COUNT;
6554 this_controller->completion_queue_entries = SCU_COMPLETION_QUEUE_COUNT;
6555 this_controller->remote_node_entries = SCI_MAX_REMOTE_DEVICES;
6556 this_controller->logical_port_entries = SCI_MAX_PORTS;
6557 this_controller->task_context_entries = SCU_IO_REQUEST_COUNT;
6558 this_controller->uf_control.buffers.count = SCU_UNSOLICITED_FRAME_COUNT;
6559 this_controller->uf_control.address_table.count= SCU_UNSOLICITED_FRAME_COUNT;
6562 scic_sds_controller_set_default_config_parameters(this_controller);
6580 SCIC_SDS_CONTROLLER_T *this_controller;
6581 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6584 this_controller, SCI_BASE_CONTROLLER_STATE_INITIALIZING);
6602 SCIC_SDS_CONTROLLER_T *this_controller;
6603 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6606 this_controller, SCI_BASE_CONTROLLER_STATE_INITIALIZED);
6624 SCIC_SDS_CONTROLLER_T *this_controller;
6625 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6628 this_controller, SCI_BASE_CONTROLLER_STATE_STARTING);
6647 SCIC_SDS_CONTROLLER_T *this_controller;
6648 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6650 scic_cb_timer_stop(object, this_controller->timeout_timer);
6655 this_controller,
6656 this_controller->phy_startup_timer
6659 this_controller->phy_startup_timer = NULL;
6678 SCIC_SDS_CONTROLLER_T *this_controller;
6679 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6682 this_controller, SCI_BASE_CONTROLLER_STATE_READY);
6687 clock_gating_unit_value = SMU_CGUCR_READ(this_controller);
6694 SMU_CGUCR_WRITE(this_controller, clock_gating_unit_value);
6698 this_controller, 0x10, 250);
6717 SCIC_SDS_CONTROLLER_T *this_controller;
6718 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6723 clock_gating_unit_value = SMU_CGUCR_READ(this_controller);
6730 SMU_CGUCR_WRITE(this_controller, clock_gating_unit_value);
6733 scic_controller_set_interrupt_coalescence(this_controller, 0, 0);
6754 SCIC_SDS_CONTROLLER_T *this_controller;
6755 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6758 this_controller, SCI_BASE_CONTROLLER_STATE_STOPPING);
6762 scic_sds_controller_stop_devices(this_controller);
6763 scic_sds_controller_stop_ports(this_controller);
6765 if (!scic_sds_controller_has_remote_devices_stopping(this_controller))
6768 &this_controller->parent.state_machine,
6789 SCIC_SDS_CONTROLLER_T *this_controller;
6790 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6792 scic_cb_timer_stop(this_controller, this_controller->timeout_timer);
6810 SCIC_SDS_CONTROLLER_T *this_controller;
6811 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6814 this_controller, SCI_BASE_CONTROLLER_STATE_STOPPED);
6818 this_controller,
6819 this_controller->timeout_timer
6821 this_controller->timeout_timer = NULL;
6824 scic_sds_controller_stop_phys(this_controller);
6827 this_controller,
6828 &this_controller->port_agent
6831 scic_cb_controller_stop_complete(this_controller, SCI_SUCCESS);
6851 SCIC_SDS_CONTROLLER_T *this_controller;
6852 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6855 sci_base_object_get_logger(this_controller),
6858 this_controller
6862 this_controller, SCI_BASE_CONTROLLER_STATE_RESETTING);
6864 scic_sds_controller_reset_hardware(this_controller);
6867 scic_sds_controller_get_base_state_machine(this_controller),
6923 SCIC_SDS_CONTROLLER_T *this_controller,
6932 abort_status = scic_sds_abort_reqests(this_controller, this_remote_device, this_port);
6938 if (this_controller->parent.error == SCI_CONTROLLER_FATAL_MEMORY_ERROR)
6939 abort_status = scic_sds_abort_reqests(this_controller, this_remote_device, this_port);
6970 SCIC_SDS_CONTROLLER_T *this_controller;
6971 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6974 this_controller, SCI_BASE_CONTROLLER_STATE_FAILED);
6976 if (this_controller->parent.error == SCI_CONTROLLER_FATAL_MEMORY_ERROR)
6977 scic_sds_terminate_all_requests(this_controller);
6979 scic_sds_controller_release_resource(this_controller);
6982 scic_cb_controller_error(this_controller,
6983 this_controller->parent.error);