drm2/radeon/evergreen_cs.c

2891 	struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;
2914 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
2923 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2929 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2930 				ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2933 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2935 					 (uintmax_t)dst_offset, radeon_bo_size(dst_reloc->robj));
2945 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
2976 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2978 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2986 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3003 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3004 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3010 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3036 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3038 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3046 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3063 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3064 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3074 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3081 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3083 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3095 						ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3120 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3122 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3130 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3152 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3153 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3163 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3170 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3172 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3196 						if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
3198 								 (uintmax_t)dst_offset + count, radeon_bo_size(dst_reloc->robj));
3201 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3203 						ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3215 						ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3216 						ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3238 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3240 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3248 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3251 						ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3271 					if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3273 							 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3276 					ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3278 					ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3285 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
3292 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3294 					 (uintmax_t)dst_offset, radeon_bo_size(dst_reloc->robj));
3297 			ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3298 			ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;