drm2/radeon/atombios_encoders.c

798 	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
903 			args.v4.ucAction = action;
904 			args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
906 				args.v4.ucPanelMode = panel_mode;
908 				args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
910 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
911 				args.v4.ucLaneNum = dp_lane_count;
913 				args.v4.ucLaneNum = 8;
915 				args.v4.ucLaneNum = 4;
917 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
923 			args.v4.acConfig.ucDigSel = dig->dig_encoder;
924 			args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
926 				args.v4.ucHPD_ID = 0;
928 				args.v4.ucHPD_ID = hpd_id + 1;
948 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1187 			args.v4.ucAction = action;
1189 				args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1191 				args.v4.asMode.ucLaneSel = lane_num;
1192 				args.v4.asMode.ucLaneSet = lane_set;
1195 					args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1197 					args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1199 					args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1203 				args.v4.ucLaneNum = dp_lane_count;
1205 				args.v4.ucLaneNum = 8;
1207 				args.v4.ucLaneNum = 4;
1210 				args.v4.acConfig.ucLinkSel = 1;
1212 				args.v4.acConfig.ucEncoderSel = 1;
1221 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1223 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1225 				args.v4.acConfig.ucRefClkSource = pll_id;
1229 				args.v4.acConfig.ucTransmitterSel = 0;
1232 				args.v4.acConfig.ucTransmitterSel = 1;
1235 				args.v4.acConfig.ucTransmitterSel = 2;
1240 				args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1243 					args.v4.acConfig.fCoherentMode = 1;
1245 					args.v4.acConfig.fDualLinkConnector = 1;