Lines Matching refs:ULONG
48 #ifndef ULONG
49 typedef unsigned long ULONG;
398 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
399 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
400 ULONG ulClockFreq:24;
402 ULONG ulClockFreq:24;
403 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
404 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
411 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
420 ULONG ulClock; //When return, [23:0] return real clock
445 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
446 ULONG ulClockFreq:24; // in unit of 10kHz
448 ULONG ulClockFreq:24; // in unit of 10kHz
449 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
483 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
484 ULONG ulClock:24; //Input= target clock, output = actual clock
486 ULONG ulClock:24; //Input= target clock, output = actual clock
487 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
516 ULONG ulClock;
542 ULONG ulReserved[2];
548 ULONG ulMemoryClock;
549 ULONG ulReserved;
557 ULONG ulTargetEngineClock; //In 10Khz unit
562 ULONG ulTargetEngineClock; //In 10Khz unit
571 ULONG ulTargetMemoryClock; //In 10Khz unit
576 ULONG ulTargetMemoryClock; //In 10Khz unit
585 ULONG ulDefaultEngineClock; //In 10Khz unit
586 ULONG ulDefaultMemoryClock; //In 10Khz unit
641 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
1371 ULONG ulReserved[2];
1630 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1645 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1647 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1650 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1652 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1661 ULONG ulDispEngClkFreq; // dispclk frequency
1678 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1752 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1783 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1792 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1972 ULONG ulTargetMemoryClock; //In 10Khz unit
2226 ULONG ulReserved;
2232 ULONG ulVotlageGpioState;
2233 ULONG ulVoltageGPioMask;
2241 ULONG ulReseved;
2335 ULONG ulSignature; // HW info table signature string "$ATI"
2348 ULONG ulSignature; // MM info table signature sting "$MMT"
2442 ULONG ulFirmwareRevision;
2443 ULONG ulDefaultEngineClock; //In 10Khz unit
2444 ULONG ulDefaultMemoryClock; //In 10Khz unit
2445 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2446 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2447 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2448 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2449 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2450 ULONG ulASICMaxEngineClock; //In 10Khz unit
2451 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2454 ULONG aulReservedForBIOS[3]; //Don't use them
2476 ULONG ulFirmwareRevision;
2477 ULONG ulDefaultEngineClock; //In 10Khz unit
2478 ULONG ulDefaultMemoryClock; //In 10Khz unit
2479 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2480 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2481 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2482 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2483 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2484 ULONG ulASICMaxEngineClock; //In 10Khz unit
2485 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2489 ULONG aulReservedForBIOS[2]; //Don't use them
2490 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2512 ULONG ulFirmwareRevision;
2513 ULONG ulDefaultEngineClock; //In 10Khz unit
2514 ULONG ulDefaultMemoryClock; //In 10Khz unit
2515 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2516 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2517 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2518 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2519 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2520 ULONG ulASICMaxEngineClock; //In 10Khz unit
2521 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2525 ULONG aulReservedForBIOS; //Don't use them
2526 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2527 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2549 ULONG ulFirmwareRevision;
2550 ULONG ulDefaultEngineClock; //In 10Khz unit
2551 ULONG ulDefaultMemoryClock; //In 10Khz unit
2552 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2553 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2554 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2555 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2556 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2557 ULONG ulASICMaxEngineClock; //In 10Khz unit
2558 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2564 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2565 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2588 ULONG ulFirmwareRevision;
2589 ULONG ulDefaultEngineClock; //In 10Khz unit
2590 ULONG ulDefaultMemoryClock; //In 10Khz unit
2591 ULONG ulReserved1;
2592 ULONG ulReserved2;
2593 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2594 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2595 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2596 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2597 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2603 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2604 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2629 ULONG ulFirmwareRevision;
2630 ULONG ulDefaultEngineClock; //In 10Khz unit
2631 ULONG ulDefaultMemoryClock; //In 10Khz unit
2632 ULONG ulReserved[2];
2633 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2634 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2635 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2636 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2637 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2643 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2644 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2647 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2648 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2661 ULONG ulReserved10[3]; // New added comparing to previous version
2682 ULONG ulBootUpEngineClock; //in 10kHz unit
2683 ULONG ulBootUpMemoryClock; //in 10kHz unit
2684 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2685 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2691 ULONG ulReserved[2];
2754 ULONG ulBootUpEngineClock; //in 10kHz unit
2755 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2756 ULONG ulBootUpUMAClock; //in 10kHz unit
2757 ULONG ulBootUpSidePortClock; //in 10kHz unit
2758 ULONG ulMinSidePortClock; //in 10kHz unit
2759 ULONG ulReserved2[6]; //must be 0x0 for the reserved
2760 ULONG ulSystemConfig; //see explanation below
2761 ULONG ulBootUpReqDisplayVector;
2762 ULONG ulOtherDisplayMisc;
2763 ULONG ulDDISlot1Config;
2764 ULONG ulDDISlot2Config;
2769 ULONG ulDockingPinCFGInfo;
2770 ULONG ulCPUCapInfo;
2775 ULONG ulHTLinkFreq; //in 10Khz
2782 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2783 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2790 ULONG ulReserved3[96]; //must be 0x0
2927 ULONG ulBootUpEngineClock; //in 10kHz unit
2928 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2929 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2930 ULONG ulBootUpUMAClock; //in 10kHz unit
2931 ULONG ulReserved1[8]; //must be 0x0 for the reserved
2932 ULONG ulBootUpReqDisplayVector;
2933 ULONG ulOtherDisplayMisc;
2934 ULONG ulReserved2[4]; //must be 0x0 for the reserved
2935 ULONG ulSystemConfig; //TBD
2936 ULONG ulCPUCapInfo; //TBD
2942 ULONG ulReserved3[4]; //must be 0x0 for the reserved
2943 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
2944 ULONG ulDDISlot2Config;
2945 ULONG ulDDISlot3Config;
2946 ULONG ulDDISlot4Config;
2947 ULONG ulReserved4[4]; //must be 0x0 for the reserved
2951 ULONG ulReserved5[4]; //must be 0x0 for the reserved
2952 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
2953 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
2954 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
2955 ULONG ulReserved6[61]; //must be 0x0
3439 ULONG ulReserved0;
3477 ULONG ulReserved[2];
3782 ULONG ulStartAddrUsedByFirmware;
3796 ULONG ulStartAddrUsedByFirmware;
4148 ULONG ulACPIDeviceEnum; //Reserved for now
4248 ULONG ulStrengthControl; // DVOA strength control for CF
4464 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
4482 ULONG ulReserved;
4493 ULONG ulGpioMaskVal; // GPIO Mask value
4503 ULONG ulMaxVoltageLevel;
4575 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
4576 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4581 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4593 ULONG ulBootUpEngineClock;
4594 ULONG ulDentistVCOFreq;
4595 ULONG ulBootUpUMAClock;
4597 ULONG ulBootUpReqDisplayVector;
4598 ULONG ulOtherDisplayMisc;
4599 ULONG ulGPUCapInfo;
4600 ULONG ulSB_MMIO_Base_Addr;
4604 ULONG ulMinEngineClock;
4605 ULONG ulSystemConfig;
4606 ULONG ulCPUCapInfo;
4614 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
4615 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
4616 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
4618 ULONG ulGMCRestoreResetTime;
4619 ULONG ulMinimumNClk;
4620 ULONG ulIdleNClk;
4621 ULONG ulDDR_DLL_PowerUpTime;
4622 ULONG ulDDR_PLL_PowerUpTime;
4631 ULONG SclkDpmBoostMargin;
4632 ULONG SclkDpmThrottleMargin;
4635 ULONG ulBoostEngineCLock;
4642 ULONG ulReserved3[15];
4754 ULONG ulPowerplayTable[128];
4766 ULONG ulBootUpEngineClock;
4767 ULONG ulDentistVCOFreq;
4768 ULONG ulBootUpUMAClock;
4770 ULONG ulBootUpReqDisplayVector;
4771 ULONG ulOtherDisplayMisc;
4772 ULONG ulGPUCapInfo;
4773 ULONG ulSB_MMIO_Base_Addr;
4777 ULONG ulMinEngineClock;
4778 ULONG ulSystemConfig;
4779 ULONG ulCPUCapInfo;
4788 ULONG ulReserved[20];
4790 ULONG ulGMCRestoreResetTime;
4791 ULONG ulMinimumNClk;
4792 ULONG ulIdleNClk;
4793 ULONG ulDDR_DLL_PowerUpTime;
4794 ULONG ulDDR_PLL_PowerUpTime;
4803 ULONG SclkDpmBoostMargin;
4804 ULONG SclkDpmThrottleMargin;
4807 ULONG ulBoostEngineCLock;
4822 ULONG ulLCDBitDepthControlVal;
4823 ULONG ulNbpStateMemclkFreq[4];
4826 ULONG ulNbpStateNClkFreq[4];
5020 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5043 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5074 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5543 ULONG ulTargetMemoryClock; //In 10Khz unit
5581 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
5798 ULONG ulDllResetClkRange;
5804 ULONG ucMemBlkId:8;
5805 ULONG ulMemClockRange:24;
5807 ULONG ulMemClockRange:24;
5808 ULONG ucMemBlkId:8;
5815 ULONG ulAccess;
5821 ULONG aulMemData[1];
5843 #define VALUE_DWORD SIZEOF ULONG
5860 ULONG ulARB_SEQDataBuf[32];
5907 ULONG ulSignature;
5925 ULONG ulReserved;
5947 ULONG ulReserved;
5948 ULONG ulFlags; // To enable/disable functionalities based on memory type
5949 ULONG ulEngineClock; // Override of default engine clock for particular memory type
5950 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
5975 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6011 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6044 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6080 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
6107 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
6129 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6171 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6202 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6234 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
6290 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
6384 ULONG Ptr32_Bit;
6429 ULONG RsvdOffScrnMemSize;
6430 ULONG RsvdOffScrnMEmPtr;
6444 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
6472 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
6473 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6488 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
6777 ULONG ulReserved;
6784 ULONG ulReserved;
6843 ULONG ulAnalogSetting[1];
6852 ULONG ulCondition;
6853 ULONG ulRegVal;
7149 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7150 ULONG ulReserved1; // must set to 0
7151 ULONG ulReserved2; // must set to 0
7165 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7166 ULONG ulMiscInfo2;
7167 ULONG ulEngineClock;
7168 ULONG ulMemoryClock;
7180 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7181 ULONG ulMiscInfo2;
7182 ULONG ulEngineClock;
7183 ULONG ulMemoryClock;
7315 ULONG ulMaxEngineClock; // For Overdrive.
7316 ULONG ulMaxMemoryClock; // For Overdrive.
7368 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
7395 ULONG ulGoldenPPID; // PPGen use only
7396 ULONG ulGoldenRevision; // PPGen use only
7408 ULONG ulTDPLimit;
7409 ULONG ulNearTDPLimit;
7410 ULONG ulSQRampingThreshold;
7412 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table
7499 ULONG ulCapsAndSettings;
7502 ULONG ulVCLK;
7503 ULONG ulDCLK;
7522 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7546 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7563 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now
7582 ULONG ulFlags;
7606 ULONG rsv2[2];
7685 ULONG ulLeakageValue;
7955 ULONG Signature;
7956 ULONG TableLength; //Length
7961 ULONG OemRevision;
7962 ULONG CreatorId;
7963 ULONG CreatorRevision;
7982 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
7983 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
7984 ULONG Reserved[4]; //0x3C
7988 ULONG PCIBus; //0x4C
7989 ULONG PCIDevice; //0x50
7990 ULONG PCIFunction; //0x54
7995 ULONG Revision; //0x60
7996 ULONG ImageLength; //0x64