Lines Matching defs:intel_dp
46 struct intel_dp {
74 * @intel_dp: DP struct
79 static bool is_edp(struct intel_dp *intel_dp)
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
86 * @intel_dp: DP struct
92 static bool is_pch_edp(struct intel_dp *intel_dp)
94 return intel_dp->is_pch_edp;
99 * @intel_dp: DP struct
103 static bool is_cpu_edp(struct intel_dp *intel_dp)
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
110 return container_of(encoder, struct intel_dp, base.base);
113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
116 struct intel_dp, base);
128 struct intel_dp *intel_dp;
133 intel_dp = enc_to_intel_dp(encoder);
135 return is_pch_edp(intel_dp);
138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
140 static void intel_dp_link_down(struct intel_dp *intel_dp);
146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
171 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
223 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
227 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
228 int max_lanes = intel_dp_max_lane_count(intel_dp);
253 struct intel_dp *intel_dp = intel_attached_dp(connector);
255 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
256 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
259 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
263 if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
325 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
327 struct drm_device *dev = intel_dp->base.base.dev;
333 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
335 struct drm_device *dev = intel_dp->base.base.dev;
342 intel_dp_check_edp(struct intel_dp *intel_dp)
344 struct drm_device *dev = intel_dp->base.base.dev;
347 if (!is_edp(intel_dp))
349 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
358 intel_dp_aux_ch(struct intel_dp *intel_dp,
362 uint32_t output_reg = intel_dp->output_reg;
363 struct drm_device *dev = intel_dp->base.base.dev;
373 intel_dp_check_edp(intel_dp);
381 if (is_cpu_edp(intel_dp)) {
478 intel_dp_aux_native_write(struct intel_dp *intel_dp,
486 intel_dp_check_edp(intel_dp);
496 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
511 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
514 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
519 intel_dp_aux_native_read(struct intel_dp *intel_dp,
529 intel_dp_check_edp(intel_dp);
539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
562 struct intel_dp *intel_dp;
572 intel_dp = data->priv;
575 intel_dp_check_edp(intel_dp);
607 ret = intel_dp_aux_ch(intel_dp,
656 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
657 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
660 intel_dp_i2c_init(struct intel_dp *intel_dp,
667 ironlake_edp_panel_vdd_on(intel_dp);
669 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
670 &intel_dp->adapter);
671 ironlake_edp_panel_vdd_off(intel_dp, false);
680 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
682 int max_lane_count = intel_dp_max_lane_count(intel_dp);
683 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
687 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
688 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
697 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, adjusted_mode))
708 intel_dp->link_bw = bws[clock];
709 intel_dp->lane_count = lane_count;
710 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
713 intel_dp->link_bw, intel_dp->lane_count,
775 struct intel_dp *intel_dp;
780 intel_dp = enc_to_intel_dp(encoder);
781 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
782 intel_dp->base.type == INTEL_OUTPUT_EDP)
784 lane_count = intel_dp->lane_count;
823 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
824 struct drm_crtc *crtc = intel_dp->base.base.crtc;
828 if (is_edp(intel_dp)) {
829 if (!is_pch_edp(intel_dp))
855 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
856 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
860 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
862 switch (intel_dp->lane_count) {
864 intel_dp->DP |= DP_PORT_WIDTH_1;
867 intel_dp->DP |= DP_PORT_WIDTH_2;
870 intel_dp->DP |= DP_PORT_WIDTH_4;
873 if (intel_dp->has_audio) {
876 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
879 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
880 intel_dp->link_configuration[0] = intel_dp->link_bw;
881 intel_dp->link_configuration[1] = intel_dp->lane_count;
885 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
886 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
887 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
892 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
894 intel_dp->DP |= DP_SYNC_HS_HIGH;
896 intel_dp->DP |= DP_SYNC_VS_HIGH;
897 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
899 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
900 intel_dp->DP |= DP_ENHANCED_FRAMING;
902 intel_dp->DP |= intel_crtc->pipe << 29;
905 intel_dp->DP |= DP_PLL_ENABLE;
907 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
909 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
910 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
911 intel_dp->DP |= intel_dp->color_range;
914 intel_dp->DP |= DP_SYNC_HS_HIGH;
916 intel_dp->DP |= DP_SYNC_VS_HIGH;
917 intel_dp->DP |= DP_LINK_TRAIN_OFF;
919 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
920 intel_dp->DP |= DP_ENHANCED_FRAMING;
923 intel_dp->DP |= DP_PIPEB_SELECT;
925 if (is_cpu_edp(intel_dp)) {
927 intel_dp->DP |= DP_PLL_ENABLE;
929 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
931 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
934 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
947 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
951 struct drm_device *dev = intel_dp->base.base.dev;
967 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
970 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
973 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
976 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
979 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
982 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
999 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1001 struct drm_device *dev = intel_dp->base.base.dev;
1005 if (!is_edp(intel_dp))
1009 if (intel_dp->want_panel_vdd)
1012 intel_dp->want_panel_vdd = true;
1014 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1019 if (!ironlake_edp_have_panel_power(intel_dp))
1020 ironlake_wait_panel_power_cycle(intel_dp);
1032 if (!ironlake_edp_have_panel_power(intel_dp)) {
1034 drm_msleep(intel_dp->panel_power_up_delay, "915edpon");
1038 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1040 struct drm_device *dev = intel_dp->base.base.dev;
1044 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1054 drm_msleep(intel_dp->panel_power_down_delay, "915vddo");
1060 struct intel_dp *intel_dp = arg;
1061 struct drm_device *dev = intel_dp->base.base.dev;
1064 ironlake_panel_vdd_off_sync(intel_dp);
1068 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1070 if (!is_edp(intel_dp))
1073 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1074 if (!intel_dp->want_panel_vdd)
1077 intel_dp->want_panel_vdd = false;
1080 ironlake_panel_vdd_off_sync(intel_dp);
1087 struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private;
1089 &intel_dp->panel_vdd_task,
1090 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1094 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1096 struct drm_device *dev = intel_dp->base.base.dev;
1100 if (!is_edp(intel_dp))
1105 if (ironlake_edp_have_panel_power(intel_dp)) {
1110 ironlake_wait_panel_power_cycle(intel_dp);
1127 ironlake_wait_panel_on(intel_dp);
1136 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1138 struct drm_device *dev = intel_dp->base.base.dev;
1142 if (!is_edp(intel_dp))
1147 if (intel_dp->want_panel_vdd)
1149 ironlake_panel_vdd_off_sync(intel_dp); /* finish any pending work */
1156 ironlake_wait_panel_off(intel_dp);
1159 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1161 struct drm_device *dev = intel_dp->base.base.dev;
1165 if (!is_edp(intel_dp))
1175 drm_msleep(intel_dp->backlight_on_delay, "915ebo");
1182 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1184 struct drm_device *dev = intel_dp->base.base.dev;
1188 if (!is_edp(intel_dp))
1196 drm_msleep(intel_dp->backlight_off_delay, "915bo1");
1227 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1232 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1236 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1246 ret = intel_dp_aux_native_write_1(intel_dp,
1258 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1260 ironlake_edp_backlight_off(intel_dp);
1261 ironlake_edp_panel_off(intel_dp);
1264 ironlake_edp_panel_vdd_on(intel_dp);
1265 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1266 intel_dp_link_down(intel_dp);
1267 ironlake_edp_panel_vdd_off(intel_dp, false);
1276 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1278 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1280 ironlake_edp_panel_vdd_on(intel_dp);
1281 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1282 intel_dp_start_link_train(intel_dp);
1283 ironlake_edp_panel_on(intel_dp);
1284 ironlake_edp_panel_vdd_off(intel_dp, true);
1285 intel_dp_complete_link_train(intel_dp);
1286 ironlake_edp_backlight_on(intel_dp);
1288 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1297 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1300 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1303 ironlake_edp_backlight_off(intel_dp);
1304 ironlake_edp_panel_off(intel_dp);
1306 ironlake_edp_panel_vdd_on(intel_dp);
1307 intel_dp_sink_dpms(intel_dp, mode);
1308 intel_dp_link_down(intel_dp);
1309 ironlake_edp_panel_vdd_off(intel_dp, false);
1311 if (is_cpu_edp(intel_dp))
1314 if (is_cpu_edp(intel_dp))
1317 ironlake_edp_panel_vdd_on(intel_dp);
1318 intel_dp_sink_dpms(intel_dp, mode);
1320 intel_dp_start_link_train(intel_dp);
1321 ironlake_edp_panel_on(intel_dp);
1322 ironlake_edp_panel_vdd_off(intel_dp, true);
1323 intel_dp_complete_link_train(intel_dp);
1325 ironlake_edp_panel_vdd_off(intel_dp, false);
1326 ironlake_edp_backlight_on(intel_dp);
1328 intel_dp->dpms_mode = mode;
1335 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1345 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1360 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1362 return intel_dp_aux_native_read_retry(intel_dp,
1418 intel_dp_voltage_max(struct intel_dp *intel_dp)
1420 struct drm_device *dev = intel_dp->base.base.dev;
1422 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1424 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1431 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1433 struct drm_device *dev = intel_dp->base.base.dev;
1435 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1461 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1470 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1480 voltage_max = intel_dp_voltage_max(intel_dp);
1484 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1489 intel_dp->train_set[lane] = v | p;
1619 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1629 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1638 intel_dp_set_link_train(struct intel_dp *intel_dp,
1642 struct drm_device *dev = intel_dp->base.base.dev;
1646 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1647 POSTING_READ(intel_dp->output_reg);
1649 intel_dp_aux_native_write_1(intel_dp,
1653 ret = intel_dp_aux_native_write(intel_dp,
1655 intel_dp->train_set,
1656 intel_dp->lane_count);
1657 if (ret != intel_dp->lane_count)
1665 intel_dp_start_link_train(struct intel_dp *intel_dp)
1667 struct drm_device *dev = intel_dp->base.base.dev;
1669 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1675 uint32_t DP = intel_dp->DP;
1678 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1679 POSTING_READ(intel_dp->output_reg);
1683 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1684 intel_dp->link_configuration,
1689 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1693 memset(intel_dp->train_set, 0, 4);
1699 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1704 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1705 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1707 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1708 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1711 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1716 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1721 if (!intel_dp_set_link_train(intel_dp, reg,
1727 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1732 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1739 for (i = 0; i < intel_dp->lane_count; i++)
1740 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1742 if (i == intel_dp->lane_count) {
1748 memset(intel_dp->train_set, 0, 4);
1754 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1762 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1764 /* Compute new intel_dp->train_set as requested by target */
1765 intel_get_adjust_train(intel_dp, link_status);
1768 intel_dp->DP = DP;
1772 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1774 struct drm_device *dev = intel_dp->base.base.dev;
1779 uint32_t DP = intel_dp->DP;
1786 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1792 intel_dp_link_down(intel_dp);
1796 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1797 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1799 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1800 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1803 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1807 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1813 if (!intel_dp_set_link_train(intel_dp, reg,
1818 if (!intel_dp_get_link_status(intel_dp, link_status))
1822 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1823 intel_dp_start_link_train(intel_dp);
1828 if (intel_channel_eq_ok(intel_dp, link_status)) {
1835 intel_dp_link_down(intel_dp);
1836 intel_dp_start_link_train(intel_dp);
1842 /* Compute new intel_dp->train_set as requested by target */
1843 intel_get_adjust_train(intel_dp, link_status);
1847 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1852 I915_WRITE(intel_dp->output_reg, reg);
1853 POSTING_READ(intel_dp->output_reg);
1854 intel_dp_aux_native_write_1(intel_dp,
1859 intel_dp_link_down(struct intel_dp *intel_dp)
1861 struct drm_device *dev = intel_dp->base.base.dev;
1863 uint32_t DP = intel_dp->DP;
1865 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1870 if (is_edp(intel_dp)) {
1872 I915_WRITE(intel_dp->output_reg, DP);
1873 POSTING_READ(intel_dp->output_reg);
1877 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1879 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1882 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1884 POSTING_READ(intel_dp->output_reg);
1888 if (is_edp(intel_dp)) {
1889 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1897 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1898 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1909 I915_WRITE(intel_dp->output_reg, DP);
1923 POSTING_READ(intel_dp->output_reg);
1930 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1931 POSTING_READ(intel_dp->output_reg);
1932 drm_msleep(intel_dp->panel_power_down_delay, "915ldo");
1936 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1938 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1939 sizeof(intel_dp->dpcd)) &&
1940 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1948 intel_dp_probe_oui(struct intel_dp *intel_dp)
1952 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1955 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1959 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1965 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1969 ret = intel_dp_aux_native_read_retry(intel_dp,
1979 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1982 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1995 intel_dp_check_link_status(struct intel_dp *intel_dp)
2000 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2003 if (!intel_dp->base.base.crtc)
2007 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2008 intel_dp_link_down(intel_dp);
2013 if (!intel_dp_get_dpcd(intel_dp)) {
2014 intel_dp_link_down(intel_dp);
2019 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2020 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2022 intel_dp_aux_native_write_1(intel_dp,
2027 intel_dp_handle_test_request(intel_dp);
2032 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2034 drm_get_encoder_name(&intel_dp->base.base));
2035 intel_dp_start_link_train(intel_dp);
2036 intel_dp_complete_link_train(intel_dp);
2041 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2043 if (intel_dp_get_dpcd(intel_dp))
2049 ironlake_dp_detect(struct intel_dp *intel_dp)
2054 if (is_edp(intel_dp)) {
2055 status = intel_panel_detect(intel_dp->base.base.dev);
2061 return intel_dp_detect_dpcd(intel_dp);
2065 g4x_dp_detect(struct intel_dp *intel_dp)
2067 struct drm_device *dev = intel_dp->base.base.dev;
2071 switch (intel_dp->output_reg) {
2090 return intel_dp_detect_dpcd(intel_dp);
2096 struct intel_dp *intel_dp = intel_attached_dp(connector);
2099 ironlake_edp_panel_vdd_on(intel_dp);
2101 ironlake_edp_panel_vdd_off(intel_dp, false);
2108 struct intel_dp *intel_dp = intel_attached_dp(connector);
2111 ironlake_edp_panel_vdd_on(intel_dp);
2113 ironlake_edp_panel_vdd_off(intel_dp, false);
2127 struct intel_dp *intel_dp = intel_attached_dp(connector);
2128 struct drm_device *dev = intel_dp->base.base.dev;
2132 intel_dp->has_audio = false;
2135 status = ironlake_dp_detect(intel_dp);
2137 status = g4x_dp_detect(intel_dp);
2141 intel_dp_probe_oui(intel_dp);
2143 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2144 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2146 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2148 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2158 struct intel_dp *intel_dp = intel_attached_dp(connector);
2159 struct drm_device *dev = intel_dp->base.base.dev;
2166 ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
2168 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2173 intel_dp->panel_fixed_mode =
2183 if (is_edp(intel_dp)) {
2185 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2186 intel_dp->panel_fixed_mode =
2188 if (intel_dp->panel_fixed_mode) {
2189 intel_dp->panel_fixed_mode->type |=
2193 if (intel_dp->panel_fixed_mode) {
2195 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2206 struct intel_dp *intel_dp = intel_attached_dp(connector);
2210 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2226 struct intel_dp *intel_dp = intel_attached_dp(connector);
2237 if (i == intel_dp->force_audio)
2240 intel_dp->force_audio = i;
2247 if (has_audio == intel_dp->has_audio)
2250 intel_dp->has_audio = has_audio;
2255 if (val == !!intel_dp->color_range)
2258 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2265 if (intel_dp->base.base.crtc) {
2266 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2293 struct intel_dp *intel_dp;
2295 intel_dp = enc_to_intel_dp(encoder);
2298 if (intel_dp->dp_iic_bus != NULL) {
2299 if (intel_dp->adapter != NULL) {
2300 device_delete_child(intel_dp->dp_iic_bus,
2301 intel_dp->adapter);
2303 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
2306 if (is_edp(intel_dp)) {
2307 struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private;
2310 &intel_dp->panel_vdd_task, NULL);
2312 &intel_dp->panel_vdd_task);
2313 ironlake_panel_vdd_off_sync(intel_dp);
2315 free(intel_dp, DRM_MEM_KMS);
2347 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2349 intel_dp_check_link_status(intel_dp);
2361 struct intel_dp *intel_dp;
2366 intel_dp = enc_to_intel_dp(encoder);
2367 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2368 intel_dp->base.type == INTEL_OUTPUT_EDP)
2369 return intel_dp->output_reg;
2396 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2407 struct intel_dp *intel_dp;
2413 intel_dp = malloc(sizeof(struct intel_dp), DRM_MEM_KMS,
2416 intel_dp->output_reg = output_reg;
2417 intel_dp->dpms_mode = -1;
2421 intel_encoder = &intel_dp->base;
2425 intel_dp->is_pch_edp = true;
2427 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2448 if (is_edp(intel_dp)) {
2450 TIMEOUT_TASK_INIT(dev_priv->tq, &intel_dp->panel_vdd_task, 0,
2451 ironlake_panel_vdd_work, intel_dp);
2494 if (is_edp(intel_dp)) {
2505 intel_dp_encoder_destroy(&intel_dp->base.base);
2536 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2537 intel_dp->backlight_on_delay = get_delay(t8);
2538 intel_dp->backlight_off_delay = get_delay(t9);
2539 intel_dp->panel_power_down_delay = get_delay(t10);
2540 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2543 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2544 intel_dp->panel_power_cycle_delay);
2547 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2549 ironlake_edp_panel_vdd_on(intel_dp);
2550 ret = intel_dp_get_dpcd(intel_dp);
2551 ironlake_edp_panel_vdd_off(intel_dp, false);
2554 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2556 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2561 intel_dp_encoder_destroy(&intel_dp->base.base);
2567 intel_dp_i2c_init(intel_dp, intel_connector, name);
2571 if (is_edp(intel_dp)) {
2576 intel_dp_add_properties(intel_dp, connector);