dev/drm/radeon_state.c

853 				     drm_radeon_clear_t * clear,
861 	unsigned int flags = clear->flags;
884 		 * 2D fill to clear the front or back buffer.
889 		OUT_RING(clear->color_mask);
920 				OUT_RING(clear->clear_color);
942 				OUT_RING(clear->clear_color);
952 	/* hyper z clear */
966 		u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
967 		    ((clear->depth_mask & 0xff) << 24);
978 			   just to the max (0xff? or actually 0x3fff?), need to take z clear
982 			   only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
983 			   other ones are ignored, and the same clear mask can be used. That's
984 			   very different behaviour than R200 which needs different clear mask
985 			   and different number of tiles to clear if hierz is enabled or not !?!
989 			/* clear mask : chooses the clearing pattern.
990 			   rv250: could be used to clear only parts of macrotiles
993 			   not clear tile (or maybe one of the bits indicates if the tile is
994 			   compressed or not), bit 2 and 3 to not clear tile 1,...,.
999 			   rv100: clearmask covers 2x8 4x1 tiles, but one clear still
1023 				   the tile cache like r100, but just needs to clear the hi-level z-buffer?
1042 					/* the number of tiles to clear */
1044 					/* clear mask : chooses the clearing pattern. */
1065 					   directly address/clear 4x4 tiles instead of 8x2 * 4x4
1066 					   macro tiles, though would still need clear mask for
1069 					/* the number of tiles to clear */
1071 					/* clear mask : chooses the clearing pattern. */
1092 					/* the number of tiles to clear */
1094 					/* clear mask : chooses the clearing pattern. */
1102 		/* TODO don't always clear all hi-level z tiles */
1108 			   just to the max (0xff? or actually 0x3fff?), need to take z clear
1120 	/* We have to clear the depth and/or stencil buffers by
1185 			tempRB3D_STENCILREFMASK = clear->depth_mask;
1261 			rb3d_stencilrefmask = clear->depth_mask;	/* misnamed field */
1329 	/* Increment the clear counter.  The client-side 3D driver must
1330 	 * wait on this value before performing the clear ioctl.  We
2122 	drm_radeon_clear_t *clear = data;
2133 	if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes,
2137 	radeon_cp_dispatch_clear(dev, clear, depth_boxes);