cxgb/common/cxgb_xgmac.c

49 	adapter_t *adap = mac->adapter;
52 	if (is_10G(adap)) {
53 		int cfg = t3_read_reg(adap, A_XGM_PORT_CFG + mac->offset);
58 	} else if (uses_xaui(adap))
74 	adapter_t *adap = mac->adapter;
77 	t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
81 	(void)t3_read_reg(adap, ctrl);
85 		t3_set_reg_field(adap, ctrl, clear[i], 0);
160 	adapter_t *adap = mac->adapter;
163 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
164 	(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
166 	t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
167 	t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
169 			 uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
170 	t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, F_UNDERUNFIX);
172 	if (uses_xaui(adap)) {
173 		if (adap->params.rev == 0) {
174 			t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
176 			if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
178 				CH_ERR(adap,
183 			t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
191 		t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
193 		t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0,
195 		t3_set_reg_field(adap, A_XGM_RX_CFG + oft, 0, F_COPYPREAMBLE |
197 		t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft,
200 		t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
201 		t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
204 	t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
209 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
210 	(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);  /* flush */
211 	if ((val & F_PCS_RESET_) && adap->params.rev) {
223 	adapter_t *adap = mac->adapter;
229 	store_mps = t3_read_reg(adap, A_MPS_CFG);
231 		t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
233 		t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
237 	t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 0);
239 	t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0);
242 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
243 	(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
246 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
247 	store = t3_read_reg(adap, A_TP_PIO_DATA);
252 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
253 	t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011);
257 	if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
259 		CH_ERR(adap, "MAC %d Rx fifo drain failed\n", idx);
264 		u32 intr = t3_read_reg(adap, A_XGM_INT_ENABLE + oft);
270 		t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
273 		(void) t3_read_reg(adap, A_XGM_PORT_CFG + oft);
274 		t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
276 		(void) t3_read_reg(adap, A_XGM_PORT_CFG + oft);
279 		t3_write_reg(adap, A_XGM_INT_ENABLE + oft, intr);
282 		t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); /*MAC in reset*/
283 		(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
286 		t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
287 		(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);  /* flush */
288 		if ((val & F_PCS_RESET_) && adap->params.rev) {
292 		t3_write_reg(adap, A_XGM_RX_CFG + oft,
298 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
299 	t3_write_reg(adap, A_TP_PIO_DATA, store);
302 	t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
306 	t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, F_ENFORCEPKT);
413 	adapter_t *adap = mac->adapter;
420 	t3_set_reg_field(adap, A_XGM_RX_CFG + oft, F_COPYALLFRAMES,
443 	t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
444 	t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
468 	adapter_t *adap = mac->adapter;
469 	unsigned port_type = adap->params.vpd.port_type[macidx(mac)];
482 		return t3_vsc7323_set_mtu(adap, mtu - 4, mac->ext_port);
486 		int err = t3_vsc8211_fifo_depth(adap,orig_mtu,macidx(mac));
492 	if (adap->params.rev >= T3_REV_B2 &&
493 	    (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
495 		v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
496 		t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
499 		reg = adap->params.rev == T3_REV_B2 ?
503 		if (t3_wait_op_done(adap, reg + mac->offset,
505 			t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
509 		t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
512 		t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
515 		t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
524 	v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
531 	t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
534 	thres = (adap->params.vpd.cclk * 1000) / 15625;
536 	if (is_10G(adap))
540 	ipg = (port_type == 9 || adap->params.rev != T3_REV_C) ? 1 : 0;
541 	t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
561 	adapter_t *adap = mac->adapter;
569 	t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
571 	t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
572 		     (pause_bits >> (adap->params.rev == T3_REV_C ? 10 : 7)));
576 		    G_RXMAXPKTSIZE(t3_read_reg(adap,
578 		val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
581 		t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
582 		t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
585 		return t3_vsc7323_set_speed_fc(adap, speed, fc, mac->ext_port);
599 		if (!uses_xaui(adap)) /* T302 */
600 			t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
603 			u32 old = t3_read_reg(adap, A_XGM_PORT_CFG + oft);
612 	val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
616 		    G_RXMAXPKTSIZE(t3_read_reg(adap,
620 	t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
622 	t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
639 	adapter_t *adap = mac->adapter;
644 		return t3_vsc7323_enable(adap, mac->ext_port, which);
647 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
648 		t3_write_reg(adap, A_TP_PIO_DATA,
649 			     adap->params.rev == T3_REV_C ?
651 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
652 		t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx,
653 				 adap->params.rev == T3_REV_C ?
656 		t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
658 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
660 		mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
662 		mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
667 		mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
675 		t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
690 	adapter_t *adap = mac->adapter;
693 		return t3_vsc7323_disable(adap, mac->ext_port, which);
696 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
705 		t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
715 	adapter_t *adap = mac->adapter;
720 		tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW);
728 		tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
731 		cfg = t3_read_reg(adap, A_MPS_CFG);
735 			t3_write_reg(adap, A_TP_PIO_ADDR,
737 			tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
766 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
767 		t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */
768 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
769 		t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */