Lines Matching defs:u_int8_t
71 u_int8_t :8; /* reserved */
72 u_int8_t sg_in_list; /* SG's in the command structure */
82 u_int8_t cdb_length; /* valid CDB bytes */
83 u_int8_t type:3;
86 u_int8_t attribute:3;
92 u_int8_t direction:2;
98 u_int8_t cdb[CISS_CDB_BUFFER_SIZE];
109 u_int8_t scsi_status;
120 u_int8_t sense_length;
138 u_int8_t res1[3];
139 u_int8_t type;
143 u_int8_t res1[2];
144 u_int8_t offense_size;
145 u_int8_t offense_offset;
149 u_int8_t sense_info[0];
182 u_int8_t periph_qualifier:3;
183 u_int8_t periph_devtype:5;
184 u_int8_t page_code;
185 u_int8_t res1;
186 u_int8_t page_length;
188 u_int8_t heads;
189 u_int8_t sectors;
190 u_int8_t fault_tolerance;
191 u_int8_t res2[3];
196 u_int8_t opcode;
197 u_int8_t reserved[5];
199 u_int8_t :8;
200 u_int8_t control;
230 u_int8_t opcode;
231 u_int8_t type;
234 u_int8_t reserved[8];
252 u_int8_t opcode;
253 u_int8_t command;
254 u_int8_t res1[2];
256 u_int8_t res2; /* reserved */
257 u_int8_t synchronous:1; /* return immediately */
258 u_int8_t ordered:1; /* return events in recorded order */
259 u_int8_t seek_to_oldest:1; /* reset read counter to oldest event */
260 u_int8_t new_only:1; /* ignore any queued events */
261 u_int8_t :4;
264 u_int8_t control;
311 u_int8_t configured_drive_flag;
312 u_int8_t spare_drive_flag;
313 u_int8_t big_physical_drive_number;
314 u_int8_t enclosure_bay_number;
332 u_int8_t previous_state;
333 u_int8_t new_state;
334 u_int8_t spare_state;
340 u_int8_t replacement_drive;
341 u_int8_t error_drive;
342 u_int8_t big_replacement_drive;
343 u_int8_t big_error_drive;
351 u_int8_t command;
352 u_int8_t failure_bus;
353 u_int8_t failure_drive;
377 u_int8_t data[64];
530 u_int8_t opcode;
531 u_int8_t log_drive;
532 u_int8_t phys_drive;
533 u_int8_t res1[3];
534 u_int8_t bmic_opcode;
536 u_int8_t res2;
547 u_int8_t drive_parameter_table[16]; /* XXX define */
548 u_int8_t fault_tolerance;
555 u_int8_t res1;
556 u_int8_t bios_disable_flag;
557 u_int8_t res2;
561 u_int8_t res3[410];
566 u_int8_t status;
579 u_int8_t res1[416];
581 u_int8_t deprecated_drive_rebuilding;
585 u_int8_t spare_configured:1;
586 u_int8_t spare_rebuilding:1;
587 u_int8_t spare_rebuilt:1;
588 u_int8_t spare_failed:1;
589 u_int8_t spare_switched:1;
590 u_int8_t spare_available:1;
591 u_int8_t res2:2;
592 u_int8_t deprecated_spare_to_replace_map[32];
594 u_int8_t media_exchanged;
595 u_int8_t cache_failure;
596 u_int8_t expand_failure;
597 u_int8_t rebuild_read_failure:1;
598 u_int8_t rebuild_write_failure:1;
599 u_int8_t res3:6;
600 u_int8_t drive_failure_map[CISS_BIG_MAP_ENTRIES / 8];
602 u_int8_t replacement_map[CISS_BIG_MAP_ENTRIES / 8];
603 u_int8_t active_spare_map[CISS_BIG_MAP_ENTRIES / 8];
604 u_int8_t spare_to_replace_map[CISS_BIG_MAP_ENTRIES];
605 u_int8_t replaced_marked_ok_map[CISS_BIG_MAP_ENTRIES / 8];
606 u_int8_t drive_rebuilding;
608 u_int8_t res4[28];
613 u_int8_t configured_logical_drives;
617 u_int8_t hardware_revision;
618 u_int8_t boot_block_revision[4];
622 u_int8_t swapped_error_cable;
624 u_int8_t bad_host_ram_addr;
625 u_int8_t cpu_revision;
626 u_int8_t res3[3];
628 u_int8_t controller_flags;
637 u_int8_t host_flags;
646 u_int8_t expand_disable_code;
655 u_int8_t scsi_chip_count;
658 u_int8_t drives_per_scsi_bus;
659 u_int8_t big_drive_present_map[CISS_BIG_MAP_ENTRIES / 8];
660 u_int8_t big_external_drive_present_map[CISS_BIG_MAP_ENTRIES / 8];
661 u_int8_t big_non_disk_map[CISS_BIG_MAP_ENTRIES / 8];
664 u_int8_t ICL_bus_map; /* Bitmap used for ICL between controllers */
665 u_int8_t redund_ctlr_modes_support; /* See REDUNDANT MODE VALUES */
666 u_int8_t curr_redund_ctlr_mode;
667 u_int8_t redund_ctlr_status;
668 u_int8_t redund_op_failure_code;
670 u_int8_t unsupported_nile_bus;
671 u_int8_t host_i2c_autorev;
672 u_int8_t cpld_revision;
673 u_int8_t fibre_chip_count;
674 u_int8_t daughterboard_type;
675 u_int8_t more_swapped_config_cable_error;
677 u_int8_t license_key_status;
678 u_int8_t access_module_status;
679 u_int8_t features_supported[12];
680 u_int8_t rec_rom_inact_rev[4]; /* Recovery ROM inactive f/w revision */
681 u_int8_t rec_rom_act_status; /* Recovery ROM flags */
682 u_int8_t pci_to_pci_status; /* PCI to PCI bridge status */
684 u_int8_t percent_write_cache; /* Percent of memory allocated to write cache */
686 u_int8_t cache_batter_count; /* Number of cache batteries */
688 u_int8_t more_controller_flags; /* Additional controller flags byte */
689 u_int8_t x_board_host_i2c_rev; /* 2nd byte of 3 byte autorev field */
690 u_int8_t battery_pic_rev; /* BBWC PIC revision */
696 u_int8_t bDdffVersion[4]; /* DDFF update engine version */
701 u_int8_t bEnclosureCount; /* Number of attached enclosures */
702 u_int8_t bExpanderCount; /* Number of expanders detected */
706 u_int8_t bInternalPortStatus[8]; /* Internal port status bytes */
707 u_int8_t bExternalPortStatus[8]; /* External port status bytes */
712 u_int8_t bLastLockup; /* Last lockup code */
713 u_int8_t bSlot; /* PCI slot according to option ROM*/
717 u_int8_t bVendorID[8]; /* Vendor ID */
718 u_int8_t bProductID[16]; /* Product ID */
727 u_int8_t MaxDevicePaths;
728 u_int8_t PowerUPNvramFlags;
733 u_int8_t FWCompileTimeStamp[24];
735 u_int8_t padding[240];
740 u_int8_t scsi_bus;
741 u_int8_t scsi_id;
748 u_int8_t inquiry_bits;
749 u_int8_t res1[2];
750 u_int8_t drive_present:1;
751 u_int8_t non_disk:1;
752 u_int8_t wide:1;
753 u_int8_t synchronous:1;
754 u_int8_t narrow:1;
755 u_int8_t wide_downgraded_to_narrow:1;
756 u_int8_t ultra:1;
757 u_int8_t ultra2:1;
758 u_int8_t SMART:1;
759 u_int8_t SMART_errors_recorded:1;
760 u_int8_t SMART_errors_enabled:1;
761 u_int8_t SMART_errors_detected:1;
762 u_int8_t external:1;
763 u_int8_t configured:1;
764 u_int8_t configured_spare:1;
765 u_int8_t cache_saved_enabled:1;
766 u_int8_t res2;
767 u_int8_t res3:6;
768 u_int8_t cache_currently_enabled:1;
769 u_int8_t cache_safe:1;
770 u_int8_t res4[5];
772 u_int8_t res5;
773 u_int8_t bay;
775 u_int8_t drive_type;
776 u_int8_t res6[393];
784 u_int8_t blinktab[256];
787 u_int8_t res2[248];
795 u_int8_t res1[510];