dev/aic7xxx/aic7xxx.c

1061 		u_int	scsirate;
1102 		scsirate = ahc_inb(ahc, SCSIRATE);
1108 			       scsirate);
1120 					       (scsirate & SINGLE_EDGE)
1773 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1778 		scsirate &= SXFR_ULTRA2;
1780 		scsirate &= SXFR;
1788 			else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1790 		} else if (scsirate == (syncrate->sxfr & SXFR)) {
1951 		u_int	scsirate;
1954 		scsirate = tinfo->scsirate;
1957 			scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1959 				scsirate |= syncrate->sxfr_u2;
1961 					scsirate |= ENABLE_CRC;
1963 					scsirate |= SINGLE_EDGE;
1967 			scsirate &= ~(SXFR|SOFS);
1978 				scsirate |= syncrate->sxfr & SXFR;
1979 				scsirate |= offset & SOFS;
1992 			ahc_outb(ahc, SCSIRATE, scsirate);
1997 		tinfo->scsirate = scsirate;
2057 		u_int	scsirate;
2060 		scsirate =  tinfo->scsirate;
2061 		scsirate &= ~WIDEXFER;
2063 			scsirate |= WIDEXFER;
2065 		tinfo->scsirate = scsirate;
2068 			ahc_outb(ahc, SCSIRATE, scsirate);
2132 		pending_hscb->scsirate = tinfo->scsirate;
2172 		ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
3094 	targ_scsirate = tinfo->scsirate;
5089 			u_int scsirate;
5093 			scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5099 				if ((scsirate & SOFS) == 0x0F) {
5104 					scsirate = (scsirate & SXFR) >> 4
5107 						 | (scsirate & WIDEXFER);
5111 				if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5113 					scsirate |= 0x1c;
5118 				    ahc_find_period(ahc, scsirate, maxsync);
5123 				if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5127 			} else if ((scsirate & SOFS) != 0) {
5128 				if ((scsirate & SXFR) == 0x40
5131 					scsirate &= ~SXFR;
5135 				    ahc_find_period(ahc, scsirate,
5144 			if ((scsirate & WIDEXFER) != 0