dev/ae/if_ae.c

192 #define	AE_WRITE_4(sc, reg, val) \
476 	AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT);
477 	AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT);
484 	AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE);
496 	AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET);
577 	AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
584 	AE_WRITE_4(sc, AE_EADDR0_REG, val);
586 	AE_WRITE_4(sc, AE_EADDR1_REG, val);
595 	AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr));
596 	AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
598 	AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
600 	AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr));
620 	AE_WRITE_4(sc, AE_IFG_REG, val);
633 	AE_WRITE_4(sc, AE_HDPX_REG, val);
641 	AE_WRITE_4(sc, AE_MASTER_REG, val);
658 	AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT);
698 	AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff);
699 	AE_WRITE_4(sc, AE_ISR_REG, 0x0);
705 	AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT);
706 	AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT);
711 	AE_WRITE_4(sc, AE_WOL_REG, 0);
722 	AE_WRITE_4(sc, AE_MAC_REG, val);
734 	AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN);
817 	AE_WRITE_4(sc, AE_MDIO_REG, val);
853 	AE_WRITE_4(sc, AE_MDIO_REG, aereg);
931 		AE_WRITE_4(sc, AE_SPICTL_REG, val);
943 	AE_WRITE_4(sc, AE_VPD_DATA_REG, 0);	/* Clear register value. */
949 	AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) &
1335 		AE_WRITE_4(sc, AE_WOL_REG, 0);
1347 			AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \
1363 			AE_WRITE_4(sc, AE_MAC_REG, val);
1366 			AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \
1368 			AE_WRITE_4(sc, AE_MAC_REG, 0);
1379 	AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val);
1382 	AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val);
1635 		AE_WRITE_4(sc, AE_MAC_REG, val);
1654 		AE_WRITE_4(sc, AE_MAC_REG, val);
1690 		AE_WRITE_4(sc, AE_MAC_REG, val);
1728 	AE_WRITE_4(sc, AE_MAC_REG, val);
1745 	AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE);
1775 	AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE);
1796 		AE_WRITE_4(sc, AE_ISR_REG, 0);
2030 	AE_WRITE_4(sc, AE_MAC_REG, val);
2061 	AE_WRITE_4(sc, AE_REG_MHT0, 0);
2062 	AE_WRITE_4(sc, AE_REG_MHT1, 0);
2064 		AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff);
2065 		AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff);
2066 		AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2083 	AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]);
2084 	AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]);
2085 	AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2179 	AE_WRITE_4(sc, AE_IMR_REG, 0);
2180 	AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);