contrib/octeon-sdk/cvmx-nand.c

1155  * @param buffer_address
1160 static inline void __cvmx_nand_setup_dma(int chip, int is_write, uint64_t buffer_address, int buffer_length)
1166     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1173     ndf_dma_cfg.s.adr = buffer_address;
1183  * @param buffer_address
1188 static void __cvmx_nand_hex_dump(uint64_t buffer_address, int buffer_length)
1190     uint8_t *buffer = cvmx_phys_to_ptr(buffer_address);
1223  * @param buffer_address
1230 static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int address_cycles, uint64_t nand_address, int nand_command2, uint64_t buffer_address, int buffer_length)
1242     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1247     if (!buffer_address)
1249     if (buffer_address & 7)
1290     __cvmx_nand_setup_dma(chip, 0, buffer_address, buffer_length);
1303     bytes = ndf_dma_cfg.s.adr - buffer_address;
1306         __cvmx_nand_hex_dump(buffer_address, bytes);
1319  * @param buffer_address
1326 int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
1333     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1340     if (!buffer_address)
1342     if (buffer_address & 7)
1353     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ, __cvmx_nand_get_address_cycles(chip), nand_address, NAND_COMMAND_READ_FIN, buffer_address, buffer_length);
1368  * @param buffer_address
1373 cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address)
1381     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1387     if (!buffer_address)
1389     if (buffer_address & 7)
1428     __cvmx_nand_setup_dma(chip, 1, buffer_address, buffer_length);
1518  * @param buffer_address
1526 int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
1533     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1538     if (!buffer_address)
1540     if (buffer_address & 7)
1545     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_ID, 1, nand_address, 0, buffer_address, buffer_length);
1547         __cvmx_nand_fixup_16bit_id_reads(cvmx_phys_to_ptr(buffer_address), buffer_length);
1560  * @param buffer_address
1567 int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length)
1573     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1578     if (!buffer_address)
1580     if (buffer_address & 7)
1587     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_PARAM_PAGE, 1, 0x0, 0, buffer_address, buffer_length);
1589         __cvmx_nand_fixup_16bit_id_reads(cvmx_phys_to_ptr(buffer_address), buffer_length);