contrib/octeon-sdk/cvmx-helper-sgmii.c

98  * @param index     Index of prot on the interface
102 static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
110     gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
112     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
117     pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
118     pcsx_linkx_timer_count_reg.u64 = cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
135     cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), pcsx_linkx_timer_count_reg.u64);
147         pcsx_anx_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
152         cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), pcsx_anx_adv_reg.u64);
161             cvmx_dprintf("SGMII%d%d: Forcing PHY mode as PHY address is not set\n", interface, index);
163             cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
170             pcsx_sgmx_an_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface));
173             cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface), pcsx_sgmx_an_adv_reg.u64);
202  * @param index     Index of prot on the interface
206 static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
223     control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
236         cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
237         if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_CONTROL_REG(index, interface), cvmx_pcsx_mrx_control_reg_t, reset, ==, 0, link_timeout))
239             cvmx_dprintf("SGMII%d: Timeout waiting for port %d to finish reset\n", interface, index);
248     cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
254         CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), cvmx_pcsx_mrx_status_reg_t, an_cpt, ==, 1, 10000))
256         //cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index);
269  * @param index     Index of prot on the interface
274 static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, int index, cvmx_helper_link_info_t link_info)
286     gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
289     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
292     if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000) ||
293         CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000))
295         cvmx_dprintf("SGMII%d: Timeout waiting for port %d to be idle\n", interface, index);
300     gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
303     pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
320             cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
321             cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
328             cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
329             cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
336             cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
338                 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); // full duplex
340                 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); // half duplex
347     cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
350     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
353     gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
357     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
376     int index;
412     for (index=0; index<num_ports; index++)
414         int ipd_port = cvmx_helper_get_ipd_port(interface, index);
415         __cvmx_helper_sgmii_hardware_init_one_time(interface, index);
486     int index;
491         for (index = 0; index < num_ports; index++)
498             gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
499             gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, index);
500             cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
503             bpid_map.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MAPX(index, interface));
505             bpid_map.s.bpid = cvmx_helper_get_bpid(interface, index);
506             cvmx_write_csr(CVMX_GMXX_BPID_MAPX(index, interface), bpid_map.u64);
509             bpid_msk.s.msk_or |= (1<<index);
510             bpid_msk.s.msk_and &= ~(1<<index);
522         for (index = 0; index < num_ports; index++)
525 	        CVMX_GMXX_TXX_APPEND(index, interface));
528             cvmx_write_csr(CVMX_GMXX_TXX_APPEND(index, interface),
533     for (index=0; index<num_ports; index++)
540         append_cfg.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(index, interface));
541         sgmii_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TXX_SGMII_CTL(index, interface));
543         cvmx_write_csr(CVMX_GMXX_TXX_SGMII_CTL(index, interface), sgmii_ctl.u64);
545         gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
547         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
569     int index = cvmx_helper_get_interface_index_num(ipd_port);
587         if (inf_mode.s.rate & (1<<index))
601     pcsx_mrx_control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
612     pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
618         int index = cvmx_helper_get_interface_index_num(ipd_port);
624         anxx_adv.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
625         mrx_status.u64 = cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG(index, interface));
626         mode_type.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
629         inband_status.u64 = cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface));
661             pcsx_mrx_status_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG(index, interface));
664                 if (__cvmx_helper_sgmii_hardware_init_link(interface, index) != 0)
669             pcsx_anx_results_reg.u64 = cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface));
724     int index = cvmx_helper_get_interface_index_num(ipd_port);
727 	__cvmx_helper_sgmii_hardware_init_link(interface, index);
732 	control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
734 	cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
735 	cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
738 	cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
739 	cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
742     return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, link_info);
762     int index = cvmx_helper_get_interface_index_num(ipd_port);
766     pcsx_mrx_control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
768     cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), pcsx_mrx_control_reg.u64);
770     pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
772     cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
774     __cvmx_helper_sgmii_hardware_init_link(interface, index);