Lines Matching defs:mii
2314 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
2356 uint64_t mii : 1;
2486 uint64_t mii : 1; /**< MII Interface Interrupt */
2528 uint64_t mii : 1;
2536 uint64_t mii : 1; /**< MII Interface Interrupt */
2576 uint64_t mii : 1;
2586 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */
2628 uint64_t mii : 1;
2637 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
2679 uint64_t mii : 1;
2750 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
2796 uint64_t mii : 1;
2803 uint64_t mii : 1; /**< MII Interface Interrupt */
2845 uint64_t mii : 1;
2852 uint64_t mii : 1; /**< MII Interface Interrupt */
2892 uint64_t mii : 1;
2935 uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
2981 uint64_t mii : 1;
2991 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
3037 uint64_t mii : 1;
3112 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
3158 uint64_t mii : 1;
3165 uint64_t mii : 1; /**< MII Interface Interrupt */
3207 uint64_t mii : 1;
3214 uint64_t mii : 1; /**< MII Interface Interrupt */
3254 uint64_t mii : 1;
3297 uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
3343 uint64_t mii : 1;
3353 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
3399 uint64_t mii : 1;
4825 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
4867 uint64_t mii : 1;
4917 uint64_t mii : 1; /**< MII Interface Interrupt */
4959 uint64_t mii : 1;
4967 uint64_t mii : 1; /**< MII Interface Interrupt */
5007 uint64_t mii : 1;
5051 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */
5093 uint64_t mii : 1;
5102 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
5144 uint64_t mii : 1;
5215 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
5260 uint64_t mii : 1;
5267 uint64_t mii : 1; /**< MII Interface Interrupt */
5309 uint64_t mii : 1;
5316 uint64_t mii : 1; /**< MII Interface Interrupt */
5356 uint64_t mii : 1;
5399 uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
5444 uint64_t mii : 1;
5454 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
5499 uint64_t mii : 1;
5573 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
5618 uint64_t mii : 1;
5625 uint64_t mii : 1; /**< MII Interface Interrupt */
5667 uint64_t mii : 1;
5674 uint64_t mii : 1; /**< MII Interface Interrupt */
5714 uint64_t mii : 1;
5757 uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
5802 uint64_t mii : 1;
5812 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
5857 uint64_t mii : 1;
7236 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
7328 uint64_t mii : 1;
7499 uint64_t mii : 1; /**< MII Interface Interrupt */
7562 uint64_t mii : 1;
7570 uint64_t mii : 1; /**< MII Interface Interrupt */
7625 uint64_t mii : 1;
7636 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt
7736 uint64_t mii : 1;
7746 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
7844 uint64_t mii : 1;
7969 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8059 uint64_t mii : 1;
8119 uint64_t mii : 1; /**< MII Interface Interrupt */
8177 uint64_t mii : 1;
8185 uint64_t mii : 1; /**< MII Interface Interrupt */
8235 uint64_t mii : 1;
8292 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt
8390 uint64_t mii : 1;
8400 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8495 uint64_t mii : 1;
8618 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8714 uint64_t mii : 1;
8723 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8799 uint64_t mii : 1;
8808 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8901 uint64_t mii : 1;