arm/arm/cpufunc_asm_xscale.S

148 	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I$ and BTB */
149 	mcr	p15, 0, r0, c7, c10, 4	/* drain write and fill buffer */
156 	mcr	p15, 0, r0, c2, c0, 0
159 	mcr	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLB */
162 	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I$ and BTB */
179 	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
180 	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
188 	mcr	p15, 0, r0, c7, c7, 0	/* flush I+D cache */
193 	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache */
198 	mcr	p15, 0, r0, c7, c6, 0	/* flush D cache */
203 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
213 	mcr	p15, 0, r0, c7, c10, 1
214 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
219 	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
311 	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache (D cleaned below) */
318 	mcr	p15, 0, r0, c7, c2, 5	/* allocate cache line */
324 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
351 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
357 	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
359 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
360 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
361 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
366 	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
368 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
369 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
387 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
394 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
408 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
409 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
410 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
417 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
430 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
431 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
438 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
451 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
452 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
459 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
469 1:	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
474 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
497 	mcr	p15, 0, r0, c2, c0, 0
500 	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */
518 	mcr	p14, 0, r0, c7, c0, 0