Lines Matching refs:mcr
43 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
47 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
48 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
53 mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
58 mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */
63 mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */
80 mcr p15, 1, r0, c15, c1, 0
90 mcr p15, 1, r0, c15, c1, 1
99 mcr p15, 1, r0, c15, c2, 0
109 mcr p15, 1, r0, c15, c1, 2
114 mcr p15, 0, r0, c1, c0, 1