vmm/io/vhpet.c

91 	} timer[VHPET_NUM_TIMERS];
108 	cap &= ~HPET_CAP_COUNT_SIZE;		/* 32-bit timer */
128 	if ((vhpet->timer[n].cap_config & msi_enable) == msi_enable)
138 	 * If the timer is configured to use MSI then treat it as if the
139 	 * timer is not connected to the ioapic.
144 	return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ROUTE) >> 9);
180 		KASSERT(pin != 0, ("vhpet timer %d irq incorrectly routed", n));
190 	return ((vhpet->timer[n].cap_config & HPET_TCNF_TYPE) != 0);
197 	return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ENB) != 0);
205 	    "timer %d is using MSI", n));
207 	if ((vhpet->timer[n].cap_config & HPET_TCNF_INT_TYPE) == 0)
218 	/* If interrupts are not enabled for this timer then just return. */
231 		lapic_intr_msi(vhpet->vm, vhpet->timer[n].msireg >> 32,
232 		    vhpet->timer[n].msireg & 0xffffffff);
255 	KASSERT(vhpet->timer[n].comprate != 0, ("hpet t%d is not periodic", n));
257 	compval = vhpet->timer[n].compval;
258 	comprate = vhpet->timer[n].comprate;
273 	vhpet->timer[n].compval = compnext;
289 	callout = &vhpet->timer[n].callout;
319 	callout_stop(&vhpet->timer[n].callout);
323 	 * had a chance to execute yet then trigger the timer interrupt
324 	 * here. Failing to do so will result in a missed timer interrupt
328 	if (vhpet->timer[n].callout_sbt < now) {
330 		    "stopping timer", n);
340 	if (vhpet->timer[n].comprate != 0)
351 	delta = (vhpet->timer[n].compval - counter) * vhpet->freq_sbt;
353 	vhpet->timer[n].callout_sbt = now + delta;
354 	callout_reset_sbt(&vhpet->timer[n].callout, vhpet->timer[n].callout_sbt,
355 	    precision, vhpet_handler, &vhpet->timer[n].arg, C_ABSOLUTE);
404 			panic("vhpet timer %d isr should not be asserted", n);
407 	oldval = vhpet->timer[n].cap_config;
417 	vhpet->timer[n].cap_config = newval;
425 	allowed_irqs = vhpet->timer[n].cap_config >> 32;
431 		vhpet->timer[n].cap_config &= ~HPET_TCNF_INT_ROUTE;
435 		vhpet->timer[n].comprate = 0;
438 	 * If the timer's ISR bit is set then clear it in the following cases:
443 	 * This is to ensure that this timer's level triggered interrupt does
447 		KASSERT(old_pin != 0, ("timer %d isr asserted to ioapic pin %d",
571 			old_compval = vhpet->timer[i].compval;
572 			old_comprate = vhpet->timer[i].comprate;
580 				val64 = vhpet->timer[i].comprate;
582 				vhpet->timer[i].comprate = val64;
583 				if ((vhpet->timer[i].cap_config &
585 					vhpet->timer[i].compval = val64;
588 				KASSERT(vhpet->timer[i].comprate == 0,
589 				    ("vhpet one-shot timer %d has invalid "
590 				    "rate %u", i, vhpet->timer[i].comprate));
591 				val64 = vhpet->timer[i].compval;
593 				vhpet->timer[i].compval = val64;
595 			vhpet->timer[i].cap_config &= ~HPET_TCNF_VAL_SET;
597 			if (vhpet->timer[i].compval != old_compval ||
598 			    vhpet->timer[i].comprate != old_comprate) {
610 			update_register(&vhpet->timer[i].msireg, data, mask);
671 			data = vhpet->timer[i].cap_config;
677 			data = vhpet->timer[i].compval;
683 			data = vhpet->timer[i].msireg;
724 	 * Initialize HPET timer hardware state.
727 		vhpet->timer[i].cap_config = allowed_irqs << 32;
728 		vhpet->timer[i].cap_config |= HPET_TCAP_PER_INT;
729 		vhpet->timer[i].cap_config |= HPET_TCAP_FSB_INT_DEL;
731 		vhpet->timer[i].compval = 0xffffffff;
732 		callout_init(&vhpet->timer[i].callout, 1);
734 		arg = &vhpet->timer[i].arg;
748 		callout_drain(&vhpet->timer[i].callout);