Lines Matching defs:NumAlignedDPRCS2Regs
37 unsigned NumAlignedDPRCS2Regs);
587 unsigned NumAlignedDPRCS2Regs,
604 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
656 unsigned NumAlignedDPRCS2Regs) const {
677 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
733 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
738 unsigned NumAlignedDPRCS2Regs,
785 .addImm(8 * NumAlignedDPRCS2Regs)));
805 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
811 if (NumAlignedDPRCS2Regs >= 6) {
821 NumAlignedDPRCS2Regs -= 4;
829 if (NumAlignedDPRCS2Regs >= 4) {
837 NumAlignedDPRCS2Regs -= 4;
841 if (NumAlignedDPRCS2Regs >= 2) {
848 NumAlignedDPRCS2Regs -= 2;
852 if (NumAlignedDPRCS2Regs) {
868 unsigned NumAlignedDPRCS2Regs) {
876 switch(NumAlignedDPRCS2Regs) {
892 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
897 unsigned NumAlignedDPRCS2Regs,
925 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
929 if (NumAlignedDPRCS2Regs >= 6) {
937 NumAlignedDPRCS2Regs -= 4;
945 if (NumAlignedDPRCS2Regs >= 4) {
952 NumAlignedDPRCS2Regs -= 4;
956 if (NumAlignedDPRCS2Regs >= 2) {
962 NumAlignedDPRCS2Regs -= 2;
966 if (NumAlignedDPRCS2Regs)
988 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
994 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
999 if (NumAlignedDPRCS2Regs)
1000 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1015 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1019 if (NumAlignedDPRCS2Regs)
1020 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1026 NumAlignedDPRCS2Regs);