CodeGen/SelectionDAG/DAGCombiner.cpp

2788         EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2791         if (ExtVT == LoadedVT &&
2792             (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2797                            LN0->getChain(), LN0->getBasePtr(), ExtVT,
2807         if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2808             (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2819             unsigned EVTStoreBytes = ExtVT.getStoreSize();
2833                            ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3820     EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3822       ExtVT = EVT::getVectorVT(*DAG.getContext(),
3823                                ExtVT, VT.getVectorNumElements());
3825          TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3827                          N0.getOperand(0), DAG.getValueType(ExtVT));
5209   EVT ExtVT = VT;
5215   // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5219     ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5226     ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5229   if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5232   unsigned EVTBits = ExtVT.getSizeInBits();
5236   if (!ExtVT.isRound())
5272       ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5305       LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
5318     unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5338                           ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
9350     EVT ExtVT = VT.getVectorElementType();
9351     EVT LVT = ExtVT;
9364       if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
9369       ExtVT = BCVT.getVectorElementType();
9378                InVec.getOperand(0).getValueType() == ExtVT &&