config/sparc/sparc.c

1111   rtx temp1, temp2, temp3, temp4, temp5;
1153 	 or	%temp1, %m44(symbol), %temp2
1154 	 sllx	%temp2, 12, %temp3
1159 	  temp2 = op0;
1165 	  temp2 = gen_reg_rtx (DImode);
1170       emit_insn (gen_setm44 (temp2, temp1, op1));
1172 			      gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1186 	 sethi	%lm(symbol), %temp2
1189 	 or	%temp4, %temp2, %temp5
1202 	  temp2 = temp;  /* op0 is _not_ allowed, see above.  */
1210 	  temp2 = gen_reg_rtx (DImode);
1217       emit_insn (gen_setlm (temp2, op1));
1222 			      gen_rtx_PLUS (DImode, temp4, temp2)));
1235 			add	%temp1, EMBMEDANY_BASE_REG, %temp2
1236 			or	%temp2, %lo(symbol), %reg  */
1242 	      temp2 = op0;
1247 	      temp2 = gen_reg_rtx (DImode);
1251 	  emit_insn (gen_embmedany_brsum (temp2, temp1));
1252 	  emit_insn (gen_embmedany_losum (op0, temp2, op1));
1256 			sethi	%hi(symbol), %temp2
1259 			or	%temp4, %temp2, %temp5
1274 	      temp2 = temp;  /* op0 is _not_ allowed, see above.  */
1282 	      temp2 = gen_reg_rtx (DImode);
1289 	  emit_insn (gen_embmedany_texthi  (temp2, op1));
1294 				  gen_rtx_PLUS (DImode, temp4, temp2)));
1405   rtx temp2 = op0;
1414 	temp2 = temp;
1419       temp2 = temp;
1424 			  gen_rtx_ASHIFT (DImode, temp2,
1469       rtx temp2 = gen_reg_rtx (DImode);
1477       emit_insn (gen_safe_HIGH64 (temp2, low_bits));
1481 				  gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1488 				  gen_rtx_PLUS (DImode, temp4, temp2)));
3071   rtx temp1, temp2, temp3, ret, o0, got, insn;
3081 	temp2 = gen_reg_rtx (SImode);
3086 	emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3089 	    emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3095 	    emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3110 	temp2 = gen_reg_rtx (SImode);
3116 	emit_insn (gen_tldm_lo10 (temp2, temp1));
3119 	    emit_insn (gen_tldm_add32 (o0, got, temp2));
3125 	    emit_insn (gen_tldm_add64 (o0, got, temp2));
3138 	temp2 = gen_reg_rtx (SImode);
3140 	emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3142 	  emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3144 	  emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3149 	temp2 = gen_reg_rtx (SImode);
3153 	emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3155 	  emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3157 	  emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3174 	temp2 = gen_reg_rtx (Pmode);
3178 	    emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3183 	    emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3185 	ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);