Lines Matching defs:of
1 /* Definitions of target machine for GNU compiler.
7 This file is part of GCC.
10 it under the terms of the GNU General Public License as published by
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 You should have received a copy of the GNU General Public License
121 TRUE if we do insn bundling instead of insn scheduling. */
129 HOST_WIDE_INT total_size; /* size of the stack frame, not including
131 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
132 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
133 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
134 HARD_REG_SET mask; /* mask of saved registers. */
135 unsigned int gr_used_mask; /* mask of registers in use as gr spill
137 int n_spilled; /* number of spilled registers. */
145 int n_input_regs; /* number of input registers used. */
146 int n_local_regs; /* number of local registers used. */
147 int n_output_regs; /* number of output registers used. */
148 int n_rotate_regs; /* number of rotating registers used. */
276 /* Table of valid machine attributes. */
532 warning (OPT_Wattributes, "invalid argument of %qs attribute",
551 error ("address area of %q+D conflicts with previous "
699 /* Return 1 if the operands of a move are ok. */
706 the validity of the underlying address, which should have been
761 Return the length of the field, or <= 0 on failure. */
769 /* Get rid of the zero bits we're shifting in. */
772 /* We must now have a solid block of 1's at bit 0. */
870 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
871 having to pointer-extend the value afterward. Other forms of address
1106 /* We really should have taken care of this offset earlier. */
1179 quantity into a pair of DImode constants. */
1278 of the postmodify entirely and fix up with an
1338 element of the target register pair is also the second element of
1420 because we do a block store to memory of unnamed arguments. */
1482 MEM operand. This requires creating an XFmode subreg of a TImode reg
1619 been reversed, and so the sense of the comparison should be inverted. */
1673 /* Extract the original sign bit of op0. */
1680 /* XOR it back into the result of the subtraction. This results
1723 rtx cmp, x, ot, of;
1730 of = operands[2-negate];
1734 if (of == CONST0_RTX (mode))
1741 x = gen_rtx_AND (mode, x, of);
1744 else if (of == CONST0_RTX (mode))
1851 /* Fill in x with the sign extension of each element in op1. */
1882 /* Fill in x1 and x2 with the sign extension of each element. */
2023 we can legitimately change the global lifetime of the GP
2024 (in the form of killing where previously live). This is
2026 value of the GP, while a direct call does, and we do not
2073 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2126 /* Because of the volatile mem read, we get an ld.acq, which is the
2127 front half of the full barrier. The end half is the cmpxchg.rel. */
2187 of insns. It also needs a valid CFG. This can't be done in
2274 to a different register. We must of course stay away from call-saved,
2321 /* Returns the number of bytes offset between the frame pointer and the stack
2322 pointer for the current function. SIZE is the number of bytes of space
2354 /* Find the size of the register stack frame. We have only 80 local
2449 /* Emit a save of BR0 if we call other functions. Do this even
2564 /* If we have an odd number of words of pretend arguments written to
2566 size of this area up to keep things 16 byte aligned. */
2591 /* Compute the initial difference between the specified pair of registers. */
2650 /* If there are more than a trivial number of register spills, we use
2657 The following data structure tracks the state of the two iterators
2665 rtx *prev_addr[2]; /* address of last memory use */
2668 int n_iter; /* number of iterators in use */
2796 insn garbage, which runs afoul of the sanity check in
2805 /* ??? Not all of the spills are for varargs, but some of them are.
2806 The rest of the spills belong in an alias set of their own. But
2839 through a pair of interleaved post_modify iterators. Just
2897 prologue. Using a prologue insn is favored compared to putting all of the
2899 to intermix instructions with the saves of the caller saved registers. In
2964 but of course we'll not have allocated that many locals. Rather than
3095 /* Locate the bottom of the register save area. */
3132 /* Handle AR regs in numerical order. All of them get special handling. */
3207 we've not split the PIC call patterns. If all of the calls
3208 are indirect, and not followed by any uses of the gp, then
3214 /* We should now be at the base of the gr/br/fr spill area. */
3227 /* Spill the rest of the BR registers. */
3255 epilogue. Using an epilogue insn is favored compared to putting all of the
3257 to intermix instructions with the saves of the caller saved registers. In
3269 /* If there is a frame pointer, then we use it instead of the stack
3287 /* Locate the bottom of the register save area. */
3376 /* We should now be at the base of the gr/br/fr spill area. */
3484 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3595 /* Don't clobber any of the registers we reserved for the prologue. */
3706 /* Emit a .spill directive, if necessary, to relocate the base of
3714 /* Emit the .body directive at the scheduled end of the prologue. */
3849 it is, return the mode of the floating point type that appears
3936 /* Return the number of words required to hold a quantity of TYPE and MODE
3951 /* Return the number of registers that should be skipped so the current
4015 If this is an SFmode aggregate, then it is possible to run out of
4020 of the argument, the last FP register, or the last argument slot. */
4053 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4061 multiple of 4 bytes in size, then this goes in a GR reg right
4082 /* Integral and aggregates go in general registers. If we have run out of
4115 the value into the high half of the general register. */
4147 /* Return number of bytes, at the beginning of the argument, that must be
4199 /* This is the original value of cum->words + offset. */
4208 If this is an SFmode aggregate, then it is possible to run out of
4213 of the argument, the last FP register, or the last argument slot. */
4231 If we have run out of FR registers, then other FP values must also go in
4408 /* In big-endian mode, we need to manage the layout of aggregates
4410 the highpart of the registers. */
4488 P Postincrement of a MEM.
4495 X A pair of floating point registers.
4793 of the multiply itself, and the latency of the instructions to
4824 /* Calculate the cost of moving data from a register in class FROM to
4908 of the f/f case when reloading (set (reg fX) (mem/v)). */
4931 register when copying between one of the registers in CLASS, and X,
4932 using MODE. A return value of NO_REGS means that no secondary register
4951 both of which are equiv to the same constant, and both which need
4988 /* This can happen because of the ior/and/etc patterns that accept FP
4994 /* This can happen because of register elimination in a muldi3 insn.
5010 /* This can happen when we take a BImode subreg of a DImode value,
5033 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5035 of this option is to mark the registers in the range from REG1 to
5048 warning (0, "value of -mfixed-range must have form REG1-REG2");
5191 /* The following collection of routines emit instruction group stop bits as
5208 /* For each register, we keep track of how it has been written in the
5216 may be written again by the complement of P (P^1) and when this happens,
5219 The result of this is that whenever an insn attempts to write a register
5253 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5254 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5255 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5256 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5287 /* Handle an access to register REGNO of type FLAGS using predicate register
5367 /* The predicates of a branch are available within the
5455 destination of the SET. */
5470 /* Subroutine of rtx_needs_barrier; this function determines whether the
5471 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5518 /* Handle an access to rtx X of type FLAGS using predicate register
5605 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5791 /* Alloc must always be the first instruction of a group.
5795 scheduler so that alloc is always reordered to the start of
5796 the current group. We could then eliminate all of the
5862 /* Clear out the state for group_barrier_needed at the start of a
5863 sequence of insns. */
5874 include the effects of INSN as a side-effect. */
5930 indicate to the optimizer that it shouldn't get rid of
5947 The second element of the vector is representative. */
6009 inserted most of the necessary stop bits. This function only
6113 /* A list of names of all available bundles. */
6135 /* Codes of the corresponding queried units: */
6153 /* The following variable value is size of the DFA state. */
6177 /* Size of spec_check_no array. */
6184 /* The following variable value is length of the arrays `clocks' and
6195 /* The following array element values are numbers of cycles should be
6200 /* The following variable value is number of data speculations in progress. */
6215 /* Return the maximum number of instructions a cpu can issue. */
6252 /* Adjust the cost of a scheduling dependency.
6253 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6388 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6483 /* We are about to issue INSN. Return the number of insns left on the
6536 /* Size of ALAT is 32. As far as we perform conservative data speculation,
6669 /* Return index of the MODE. */
6757 If current pattern of the INSN already provides TS speculation, return 0. */
6820 /* We should use MEM's mode since REG's mode in presence of ZERO_EXTEND
6842 /* Number of patterns for each speculation mode. */
6867 /* If GEN_P is true, calculate the index of needed speculation check and return
6870 If GEN_P is false, just calculate the index of needed speculation check. */
6957 /* ld.sa can be used instead of ld.s to avoid basic block splitting. */
7136 speculative load in the RESOLVED_DEPS list of INSN.
7217 /* The following describes state of insn bundling. */
7229 int cost; /* cost of the state in cycles */
7230 int accumulated_insns_num; /* number of all previous insns including
7232 int branch_deviation; /* deviation of previous branches from 3rd slots */
7245 /* The unique number of next bundle state. */
7319 /* Hash table of the bundle states. The key is dfa_state and insn_num
7320 of the bundle states. */
7324 /* The function returns hash of BUNDLE_STATE. */
7411 with different number of inserted nops. */
7590 /* The function returns code of a possible template for given position
7591 and state. The function should be called only with 2 values of
7593 templates containing F insns at the end of the template search
7598 the use of F-unit instructions unless they're really needed. */
7688 to following nops, as br.call sets rp to the address of following
7722 inserted nops. Nondeterminism of the automata permits follows
7733 start of simulated processor cycle from insn scheduling (insn
7736 Simple implementation of insn bundling would create enormous
7737 number of possible insn sequences satisfying information about new
7747 When we reach the end of EBB (extended basic block), we choose the
7783 /* First (forward) pass -- generation of bundle states. */
7820 /* Forward pass: generation of bundle states. */
7874 /* This structure is taken from generated code of the
7968 /* We are at the end of the window -- find template(s) for
7996 /* We are at the start of a bundle: emit the template
8077 /* Now we are searching for a template of the bundle in
8078 which the MM-insn is placed and the position of the
8102 /* Some check of correctness: the stop is not at the
8104 and the MM-insn is not at the start of bundle with
8139 /* Put the MM-insn in the same slot of a bundle with the
8143 of nops. */
8158 /* The following function is called at the end of scheduling BB or
8305 /* The following function returns TRUE if PRODUCER (of type ilog or
8306 ld) produces address for CONSUMER (of type st or stf). */
8329 /* The following function returns TRUE if PRODUCER (of type ilog or
8330 ld) produces address for CONSUMER (of type ld or fld). */
8412 grabbing the entire block of predicate registers. */
8426 returns, and complain about uses of call-clobbered predicates after
8626 /* Conditional return patterns can't represent the use of `b0' as
8670 instead of addl,ld8/ld8. This makes the code bigger, but should make the
8720 /* True if we need a copy_state command at the start of the next block. */
8769 separate region for the very end of the epilogue, so refrain from
8774 /* The function emits unwind directives for the start of an epilogue. */
8779 /* If this isn't the last block of the function, then we need to label the
8780 current state, and copy it back in at the start of the next block. */
9186 most significant bits of the stack slot. */
9231 modes of word_mode and larger. Rename the TFmode libfuncs using the
9332 /* These functions are not part of the HPUX TFmode interface. We
9333 use them instead of _U_Qfcmp, which doesn't work the way we
9400 structure type and that the address of that type should be passed
9449 /* Mark the end of the (empty) prologue. */
9552 /* Run just enough of rest_of_compilation to get the insns emitted.
9635 because the stub clobbers r15 as per 5.3.6 of the psABI.
9725 /* Return the mangling of TYPE if it is an extended fundamental type. */
9734 /* On HP-UX, "e" is not available as a mangling of __float80 so use
9784 /* Implement overriding of the optimization options. */