Lines Matching defs:to
22 along with GAS; see the file COPYING. If not, write to the Free
78 remain, leading to rld crashes. */
96 For ELF target, default to Octeon load/store instructions.
97 For Linux target, default to MIPS load/store instructions. */
151 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
173 /* True for mips16 instructions that jump to an absolute address. */
177 /* The ABI to use. */
204 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 /* Enabled Application Specific Extensions (ASEs). These are set to -1
225 /* Non-zero if we should not permit the $at ($1) register to be used
244 to 32 bit. This is initially determined when -mgp32 or -mfp32
261 /* This is the struct we use to hold the current set of options. Note
262 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
263 -1 to indicate that they have not been initialized. */
388 /* Return true if ISA supports move to/from high part of a 64-bit
448 which write to the HI and LO registers.
450 According to MIPS specifications, MIPS ISAs I, II, and III need
456 MIPS64 and later ISAs to have the interlocks, plus any specific
471 /* Whether the processor uses hardware interlocks to protect reads
473 require nops to be inserted. This applies to instructions marked
480 /* Whether the processor uses hardware interlocks to avoid delays
482 nops to be inserted. This applies to instructions marked
483 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
495 /* Whether the processor uses hardware interlocks to protect reads
497 thus does not require nops to be inserted. This applies to
520 point registers which just happen to alias the double width destination
543 possible, we can skip the relaxation stuff that tries to produce
547 This function can only provide a guess, but it seems to work for
548 gcc output. It needs to guess right for gcc, otherwise gcc
567 a line. If the line seems to have the form '# 123 filename'
578 /* Chars that can be used to separate mant from exp in floating point nums */
586 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
587 changed in read.c . Ideally it shouldn't have to know about it at all,
595 /* When outputting SVR4 PIC code, the assembler needs to know the
596 offset in the stack frame from which to restore the $gp register.
614 .frame pseudo-op. This is needed to implement .cprestore. */
621 /* To output NOP instructions correctly, we need to keep information
624 /* Whether we are optimizing. The default value of 2 means to remove
626 of 1 means to not swap branches. A value of 0 means to always
630 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
631 equivalent to seeing no -g option at all. */
634 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
637 /* The maximum number of NOPs needed to fill delay slots. */
644 We need to look back MAX_NOPS instructions when filling delay slots
645 or working around processor errata. We need to look back one
646 instruction further if we're thinking about using history[0] to
656 /* If this is set, it points to a frag holding nop instructions which
658 nops turn out to be unnecessary, the size of the frag can be
674 has only 16 bits of space to store an addend. This means that in
675 order for the linker to handle carries correctly, it must be able
676 to locate both the HI and the LO relocation. This means that the
679 In order to implement this, we keep track of each unmatched HI
702 /* Map normal MIPS register numbers to mips16 register numbers. */
714 /* Map mips16 register numbers to normal MIPS register numbers. */
744 /* We don't relax branches by default, since this causes us to expand
746 fail to compute the offset before expanding the macro to the most
753 they refer to. For example, when generating position-dependent code,
754 a macro that refers to a symbol may have two different expansions,
776 is longer than its first. This refers to the macro as a whole,
787 The frag's "opcode" points to the first fixup for relaxable code.
830 the branch would be more efficient, it would be very tricky to do
831 correctly, because we'd have to introduce a variable frag *after*
835 to be common, anyway.
852 It would be possible to generate a shorter sequence by losing the
895 object. Therefore, we need to support this type of relaxation at
897 use the high bit of the subtype field to distinguish these cases.
904 whether the fragment is considered to be extended or not. We also
905 store whether this is known to be a branch to a different section,
906 whether we have tried to relax this frag yet, and whether we have
985 the first fixup that refers to relaxable code.) */
997 /* Global variables used to decide whether a macro needs a warning. */
1076 /* Table and functions used to map between CPU/ISA names, and
1107 specific to the type of debugging information being generated, and
1113 not MIPS CPU specific, but are also not specific to the object file
1114 format. This file is probably the best place to define them, but
1139 /* Relatively generic pseudo-ops that happen to be used on MIPS
1264 /* The default target format to use. */
1364 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1383 /* Add INSN to the end of the output. */
1392 /* Start a variant frag and move INSN to the start of the variant part,
1407 position FIRST. Neither FIRST nor N need to be clipped. */
1435 the idea is to make it obvious at a glance that each errata is
1740 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1755 /* Advance to next token if a register was recognised. */
1853 /* We add all the general register names to the symbol table. This
1887 to 16 byte boundaries. When configured for an embedded ELF
2039 need a matching %lo() when applied to local symbols. */
2048 all GOT16 relocations evaluate to "G". */
2089 need to distinguish reading both $f0 and $f1 or just one of
2090 them. Note that we don't have to check the other way,
2163 /* Move all labels in insn_labels to the current insertion point. */
2206 /* Mark instruction labels in mips16 mode. This permits the linker to
2209 order to generate the right sort of code. We will make them even
2212 to make them odd again. */
2234 references to it which will be patched up by the linker, and
2289 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2321 /* This function needs to know which pinfo flags are set for INSN2
2384 Need to modify this to include knowledge about
2389 /* Handle cases where INSN1 writes to a known general coprocessor
2434 /* Return the number of nops that would be needed to work around the
2444 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2507 might be added to HISTORY. Return the largest number of nops that
2557 ADDRESS_EXPR is an operand of the instruction to be used with
2605 argument to frag_grow here must be at least as large
2606 as the argument to all other calls to frag_grow in
2607 this file. We don't have to worry about being in the
2641 /* Allow this instruction to replace one of the nops that was
2642 tentatively added to prev_nop_frag. */
2650 /* The value passed to dwarf2_emit_insn is the distance between
2653 we want to use ISA-encoded addresses, so we pass -1 for an
2691 /* We need to set up a variant frag. */
2706 /* Make sure there is enough room to swap this instruction with
2780 as_bad (_("jump to misaligned address (0x%lx)"),
2787 as_bad (_("jump to misaligned address (0x%lx)"),
2797 as_bad (_("branch to misaligned address (0x%lx)"),
2884 Note that the ABI allows the second relocation to be
2895 /* Use fx_tcbit to mark compound relocs. */
2924 /* We don't keep enough information to sort these cases out.
2927 instruction. May want to add this support in the future. */
2956 /* Filling the branch delay slot is more complex. We try to
2987 there are any branches to anything other than a
2992 This does not apply to the mips16, which uses variant
3003 complicates trap handlers to have the trap
3040 branches write only to RD or to $31). */
3063 branches only write to RD or to $31). */
3105 /* We could do even better for unconditional branches to
3128 /* Add the delay slot instruction to the end of the
3131 the latter, move it backwards to cover the gap. */
3156 into the delay slot, and increment the branch to jump to
3217 nops that turn out not to be needed. */
3235 /* Move on to a new frag, so that it is safe to simply
3256 /* Commit to inserting prev_nop_frag_required nops and go back to
3350 a pointer to the count of instructions created so far, an
3351 expression, the name of the instruction to build, an operand format
3550 * This allows macro() to pass an immediate expression for
3559 as_bad (_("branch to misaligned address (0x%lx)"),
3742 * Generate a "jalr" instruction with a relocation hint to the called
3816 /* Generate a sequence of instructions to do a load or store from a constant
3844 to handle the complete offset. */
3855 * Generates code to set the $at register to true (one)
3890 majority of values than a simple loop to count the bits:
3965 * This routine generates the least number of instructions necessary to load
3984 /* We can handle 16 bit signed values with an addiu to
3985 $zero. No need to ever use daddiu here, since $zero and
3992 /* We can handle 16 bit unsigned values with an ori to
4138 /* This instruction will set the register to be all
4223 /* If this is a reference to a GP relative symbol, we want
4306 /* If this is a reference to an external symbol, we want
4367 /* This is the large GOT case. If this is a reference to an
4373 Otherwise, for a reference to a local symbol in old ABI, we want
4425 instruction stream does not refer to $gp, and so will not
4462 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4474 a sequence to add a 32-bit offset using a scratch register. */
4525 /* Set mips_optimize around the lui instruction to avoid
4541 * of these macros are simple and are similar to each other. These could
5165 /* We want to close the noreorder block as soon as possible, so
5175 /* We want to close the noreorder block as soon as possible, so
5277 /* We want to close the noreorder block as soon as possible, so
5287 /* We want to close the noreorder block as soon as possible, so
5305 zero, we then add a base register to it. */
5308 as_warn (_("dla used to load 32-bit register"));
5311 as_warn (_("la used to load 64-bit address"));
5343 /* If this is a reference to a GP relative symbol, we want
5435 /* If this is a reference to an external symbol, and there
5445 If we have a small constant, and this is a reference to
5454 If we have a large constant, and this is a reference to
5477 /* We're going to put in an addu instruction using
5507 /* If we are going to add in a base register, and the
5510 we want to load the constant into AT, we add our
5530 /* If this is a reference to an external, and there is no
5537 If we have a small constant, and this is a reference to
5542 If we have a large constant, and this is a reference to
5549 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5572 /* If we are going to add in a base register, and the
5575 we want to load the constant into AT, we add our
5636 /* This is the large GOT case. If this is a reference to an
5650 If we have a small constant, and this is a reference to
5662 If we have a large constant, and this is a reference to
5696 /* We're going to put in an addu instruction using
5713 /* If we are going to add in a base register, and the
5716 we want to load the constant into AT, we add our
5757 so if the symbol turns out to not be external, and
5772 /* We set breg to 0 because we have arranged to add
5792 /* This is the large GOT case. If this is a reference to an
5802 If we have a small constant, and this is a reference to
5809 If we have a large constant, and this is a reference to
5821 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5852 /* If we are going to add in a base register, and the
5855 we want to load the constant into AT, we add our
5902 requires an absolute address. We convert it to a b
5911 generating PIC code they expand to multi-instruction
5922 as_warn (_("MIPS PIC call to register other than $25"));
5959 /* If this is a reference to an external symbol, and we are
5985 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6321 /* If this is a reference to a GP relative symbol, and there
6330 If we have a base register, and this is a reference to a
6476 /* If this is a reference to an external symbol, we want
6490 If there is a base register, we add it to $tempreg before
6493 16 bits, because we have no way to load the upper 16 bits
6530 /* If this is a reference to an external symbol, we want
6540 If there is a base register, we add it to $tempreg before
6543 16 bits, because we have no way to load the upper 16 bits
6577 /* If this is a reference to an external symbol, we want
6725 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6799 to adjust when loading from memory. */
6805 /* FIXME: A possible overflow which I don't know how to deal
6814 * The MIPS assembler seems to check for X_add_number not
6899 to adjust when loading from memory. We set coproc if we must
6908 /* If this is a reference to a GP relative symbol, we want
6919 If there is a base register, we add it to $at after the
6944 /* Set mips_optimize to 2 to avoid inserting an
6959 subtract it out, and then subtract another 4 to make
6961 will come out right because we are going to add 4 to
6964 If we have a symbol, then we don't want to include
6993 /* If this is a reference to an external symbol, we want
7003 If there is a base register we add it to $at before the
7016 /* Set mips_optimize to 2 to avoid inserting an undesired
7042 /* If this is a reference to an external symbol, we want
7054 If there is a base register we add it to $at before the
7079 /* Set mips_optimize to 2 to avoid inserting an undesired
7103 /* Set mips_optimize to 2 to avoid inserting an undesired
7142 This will get expanded to
7171 /* New code added to support COPZ instructions.
7173 R4000 uses interlocks to handle coproc delays.
7174 Other chips (like the R3000) require nops to be inserted for delays.
7177 In order to fill delay slots for non-interlocked chips,
7178 we must have a way to specify delays based on the coprocessor.
7185 If an itbl is provided to interpret cop instructions,
7221 We may want to have the assembler assemble this value,
7224 Would it be more efficient to use mask (id) here? */
7286 not trying to be that fancy. GCC should do this for us
7546 to adjust when storing to memory. */
7848 /* Expand the ulh to "lb, lbu, ins" instead of "lb, lbu, sll, ori". */
7886 /* For small variables the compiler uses gp_rel to load the value of
7888 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
7935 /* For small variables the compiler uses gp_rel to load the value of
7937 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
8025 /* For small variables the compiler uses gp_rel to load the value of
8027 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
8063 /* For small variables the compiler uses gp_rel to load the value of
8065 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
8168 but I don't see how to do the comparisons without a temporary
8549 offset_reloc to the type of relocation to do if one of the operands
8572 /* If the instruction contains a '.', we first try to match an instruction
8579 the call to hash_find. Save the character we replaced just in case we
8580 have to re-parse the instruction. */
8590 this time with just the instruction up to, but not including the
8598 /* Scan up to the first '.' or whitespace. */
8630 we want to allow jalx if -mips16 was specified
9207 * According to the manual, if the shift amount is greater
9424 * to figure out where it goes in the instruction. */
9572 /* This is like 'Z', but also needs to fix the MDMX
9666 This means we don't have to worry about backing out
9682 The code below needs to know whether the target register
9720 copied to FPRs if the GPRs are at least as wide
9731 /* The value is simple enough to load with a couple of
9733 imm_expr to the high order 32 bits and offset_expr to
9734 the low order 32 bits. Otherwise, set imm_expr to
9786 /* Switch to the right section. */
9820 /* Set the argument to the current address in the
9832 /* Switch back to the original section. */
10036 global variables imm_reloc or offset_reloc to the type of
10037 relocation to do if one of the operands is an address expression.
10374 /* We need to relax this instruction. */
10392 /* What we thought was an expression turned out to
10411 /* We need to relax this instruction. */
10429 /* We need to relax this instruction. */
10593 /* Add $ra to insn. */
10778 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10780 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10932 /* Return true if *STR points to a relocation operator. When returning true,
10982 On exit, EXPR_END points to the first character after the expression. */
10994 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11052 text symbols are handled. We don't bother to handle complex
11089 return _("bad call to md_atof");
11328 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11330 we have to defer parsing the -march and -mtune arguments in order
11331 to handle 'from-abi' correctly, since the ABI might be specified
11583 /* When generating ELF code, we permit -KPIC and -call_shared to
11584 select SVR4_PIC, and -non_shared to select no PIC. This is
11585 intended to be compatible with Irix 5. */
11606 /* The -xgot option tells the assembler to use 32 bit offsets
11736 /* Set up globals to generate code for the ISA or processor
11779 Similar code was added to GCC 3.3 (see override_options() in
11837 Restrict ourselves to 32-bit registers if that's all the
11851 registers would lead to spurious "register must be even" messages.
11986 /* This is called before the symbol table is processed. In order to
11988 However, in other cases, we want to discard them. If we were
11990 mean that gcc is smuggling debugging information through to
12012 (a) it refers to the same symbol; and
12016 (b) allows us to cope with code like:
12022 if the user knows that adding 2 to "foo" will not induce a carry to
12026 following rules to distinguish them:
12044 allows careful users to avoid it.
12048 It therefore makes sense to choose the last matching low-part
12050 to code that way. */
12065 /* If a GOT16 relocation turns out to be against a global symbol,
12066 there isn't supposed to be a matching LO. */
12071 /* Check quickly whether the next fixup happens to be a matching %lo. */
12077 /* Set HI_POS to the position of this relocation in the chain.
12078 Set LO_POS to the position of the chosen low-part relocation.
12079 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12110 versions of gcc have been known to emit dead "lui ...%hi(...)"
12126 We have to prevent gas from dropping them. */
12144 /* Apply a fixup to the object file. */
12179 exceptions is to generate a relocation against STN_UNDEF and
12180 leave everything up to the linker. */
12229 /* Nothing needed to do. The value comes from the reloc entry. */
12268 may be safe to remove, but if so it's not obvious. */
12285 _("Branch to misaligned address (%lx)"), (long) *valP);
12287 /* We need to save the bits in the instruction since fixup_segment()
12315 we can convert it to an absolute jump instruction. */
12329 and there's nothing we can do to fix this instruction
12370 /* Align the current frag to a given power of two. The MIPS assembler
12374 mips_align (int to, int fill, symbolS *label)
12377 frag_align (to, fill, 0);
12378 record_alignment (now_seg, to);
12387 /* Align to a given power of two. .align 0 turns off the automatic
12398 to the aligned address.
12402 issues an error on attempt to assemble an improperly aligned data item.
12442 /* The ELF backend needs to know that we are changing sections, so
12445 as it would not be appropriate to use it in the section changing
12548 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12549 traditionally had to fall back on the more common @progbits instead.
12552 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12556 Even so, we shouldn't force users of the MIPS .section syntax to
12558 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12616 /* Handle .globl. We need to override it because on Irix 5 you are
12617 permitted to say
12619 where foo is an undefined symbol, to mean that foo should be
12620 considered to be the address of a function. */
12720 /* This structure is used to hold a stack of .set values. */
12870 /* Permit the user to change the ISA and architecture on the fly.
12871 Needless to say, misuse can cause serious problems. */
12958 /* If we're changing the reorder mode we need to handle
12984 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12990 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12991 .option pic2. It means to generate SVR4 PIC calls. */
13017 The -mno-shared option changes this to:
13046 /* If we need to produce a 64-bit address, we are better off using
13320 code. It sets the offset to use in gp_rel relocations. */
13440 /* Add $gp to the register named as an argument. */
13450 mips16 mode. This permits the linker to handle them specially,
13452 them odd for the duration of the assembly, in order to generate the
13455 debugger and the disassembler. The linker knows to make them odd
13466 /* Handle a .stabn directive. We need these in order to mark a label
13503 as_bad ("ignoring attempt to redefine symbol %s",
13529 to parse .frame. The argument is non-zero if this is the frame
13556 /* We don't need to align ELF sections to the full alignment.
13557 However, Irix 5 may prefer that we align them at least to a 16
13558 byte boundary. We don't bother to align the sections if we
13571 example, a symbol may later become defined which appeared to be
13649 /* Handle the case of a symbol equated to another symbol. */
13654 /* It's possible to get a loop here in a badly written program. */
13735 branch to a different section, we mark it as such. If SEC is
13736 NULL, and the frag is not marked, then it must be a branch to
13754 _("unsupported PC relative reference to different section"));
13761 a forward branch to another frag, as the forward frag
13769 yet adjusted the symbol fragment fr_address. We want to add
13770 in STRETCH in order to get a better estimate of the address.
13779 defined in what appears to be an earlier frag. FIXME:
13781 a maximum number of bytes to skip when doing an
13835 instruction, this can lead to a loop, so we arrange to always
13845 /* If we are about to mark a frag as extended because the value
13855 frag as extended if it was small, and is about to become
13879 worst-case length is computed, with UPDATE being used to indicate
13881 branch is to be computed. */
13943 encoded in the subtype information. For the mips16, we have to
13960 /* We don't want to modify the EXTENDED bit here; it might get us
13983 /* This is called to see whether a reloc against a defined symbol
14002 need to recalculate the complete offset in order to correctly identify
14006 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14008 this, it seems better not to force the issue, and instead keep the
14019 to a floating-point stub. The same is true for non-R_MIPS16_26
14027 resolve to T must also be against F. We therefore have the following
14055 targets.) This approach is a little simpler than trying to detect
14068 /* Translate internal representation of relocation info to BFD target
14094 reloc handling. What's worse, for COFF (as opposed to
14104 entry to be used in the relocation's section offset. */
14183 because, if there are linker relaxations, we're going to
14250 current instruction to branch to. */
14257 /* How many bytes in instructions from here to the end? */
14260 /* Convert to instruction count. */
14277 /* Compute the PC offset from the current instruction to
14281 /* How many bytes in instructions from here to the end? */
14283 /* Convert to instruction count. */
14285 /* Don't decrement i, because we want to branch over the
14481 (by marking them as done) if we're going to use the second
14493 we're going to use the first sequence, otherwise adjust their
14494 addresses to account for the relaxation. */
14522 back to even for the convenience of the debugger. */
14632 /* We may need to define a new flag for DSP ASE, and set this flag when
14635 /* We may need to define a new flag for MT ASE, and set this flag when
14661 /* Nothing to do for N64_ABI. */
14808 /* Versions of GCC up to 3.1 start files with a ".file"
14811 after 3.1 in order to support DWARF-2 on MIPS. */
14873 /* Create an expression to calculate the size of the function. */
14976 We can't use the ecoff routines because they make reference to the ecoff
15020 make reference to the ecoff symbol table (in the mdebug section). */
15215 hoping to find a number there too. */
15241 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15245 Treat NO_ABI like the EABIs. One reason to do this is that the
15343 -G NUM allow referencing objects up to NUM bytes\n\
15365 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15366 -no-mCPU don't generate code specific to CPU.\n\
15400 --[no-]construct-floats [dis]allow floating point values to be constructed\n\