pexpert/arm/pe_s5l8930x.c

57 #define HwReg(x) *((volatile unsigned long*)(x))
105         HwReg(gS5L8930XClockGateBase + __register) = HwReg(gS5L8930XClockGateBase + __register) | 0xF;
107         HwReg(gS5L8930XClockGateBase + __register) = HwReg(gS5L8930XClockGateBase + __register) & ~0xF;
113     while ((HwReg(gS5L8930XClockGateBase + __register) & 0xF) != ((HwReg(gS5L8930XClockGateBase + __register) >> 4) & 0xF))
141     while (HwReg(gS5L8930XUartBase + UFSTAT) & UART_UFSTAT_TXFIFO_FULL)
144     HwReg(gS5L8930XUartBase + UTXH) = c;
154     uint32_t ufstat = HwReg(gS5L8930XUartBase + UFSTAT);
159         return HwReg(gS5L8930XUartBase + URXH);
218     HwReg(gS5L8930XUartBase + ULCON) = UART_8BITS;
223     HwReg(gS5L8930XUartBase + UCON) = ((UART_UCON_MODE_IRQORPOLL << UART_UCON_RXMODE_SHIFT) | (UART_UCON_MODE_IRQORPOLL << UART_UCON_TXMODE_SHIFT));
228     HwReg(gS5L8930XUartBase + UCON) = (HwReg(gS5L8930XUartBase + UCON) & (~UART_CLOCK_SELECTION_MASK)) | (1 << UART_CLOCK_SELECTION_SHIFT);
235     HwReg(gS5L8930XUartBase + UBRDIV) = (HwReg(gS5L8930XUartBase + UBRDIV) & (~UART_DIVVAL_MASK)) | divisorValue;
240     HwReg(gS5L8930XUartBase + UFCON) = UART_FIFO_RESET_RX | UART_FIFO_RESET_TX;
245     HwReg(gS5L8930XUartBase + UFCON) = UART_FIFO_ENABLE;
269     HwReg(gS5L8930XVic0Base + VICINTENCLEAR) = 0xFFFFFFFF;
270     HwReg(gS5L8930XVic1Base + VICINTENCLEAR) = 0xFFFFFFFF;
271     HwReg(gS5L8930XVic2Base + VICINTENCLEAR) = 0xFFFFFFFF;
272     HwReg(gS5L8930XVic3Base + VICINTENCLEAR) = 0xFFFFFFFF;
274     HwReg(gS5L8930XVic0Base + VICINTENABLE) = 0;
275     HwReg(gS5L8930XVic1Base + VICINTENABLE) = 0;
276     HwReg(gS5L8930XVic2Base + VICINTENABLE) = 0;
277     HwReg(gS5L8930XVic3Base + VICINTENABLE) = 0;
282     HwReg(gS5L8930XVic0Base + VICINTSELECT) = 0;
283     HwReg(gS5L8930XVic1Base + VICINTSELECT) = 0;
284     HwReg(gS5L8930XVic2Base + VICINTSELECT) = 0;
285     HwReg(gS5L8930XVic3Base + VICINTSELECT) = 0;
290     HwReg(gS5L8930XVic0Base + VICSWPRIORITYMASK) = 0xFFFF;
291     HwReg(gS5L8930XVic1Base + VICSWPRIORITYMASK) = 0xFFFF;
292     HwReg(gS5L8930XVic2Base + VICSWPRIORITYMASK) = 0xFFFF;
293     HwReg(gS5L8930XVic3Base + VICSWPRIORITYMASK) = 0xFFFF;
300         HwReg(gS5L8930XVic0Base + VICVECTADDRS + (i * 4)) = (0x20 * 0) + i;
301         HwReg(gS5L8930XVic1Base + VICVECTADDRS + (i * 4)) = (0x20 * 1) + i;
302         HwReg(gS5L8930XVic2Base + VICVECTADDRS + (i * 4)) = (0x20 * 2) + i;
303         HwReg(gS5L8930XVic3Base + VICVECTADDRS + (i * 4)) = (0x20 * 3) + i;
329     HwReg(gS5L8930XVic0Base + VICINTENABLE) = HwReg(gS5L8930XVic0Base + VICINTENABLE) | (1 << 5) | (1 << 6);
352     uint32_t current_irq = HwReg(gS5L8930XVic0Base + VICADDRESS);
375         HwReg(gS5L8930XVic0Base + VICADDRESS) = 0;
414     uint64_t ret = (uint64_t) ((uint32_t) 0xFFFFFFFF - (uint32_t) HwReg(gS5L8930XTimerBase + TIMER0_VAL));
431         HwReg(gS5L8930XTimerBase + TIMER0_CTRL) = 2;
432         HwReg(gS5L8930XTimerBase + TIMER0_CTRL) = 0;
434         HwReg(gS5L8930XTimerBase + TIMER0_VAL) = 0xFFFFFFFF;
435         HwReg(gS5L8930XTimerBase + TIMER0_CTRL) = 3;
436         HwReg(gS5L8930XTimerBase + TIMER0_CTRL) = 1;
437         HwReg(gS5L8930XTimerBase + TIMER0_VAL) = clock_decrementer;
496     HwReg(gS5L8930XPmgrBase + 0x2C) = 0;
497     HwReg(gS5L8930XPmgrBase + 0x24) = 1;
498     HwReg(gS5L8930XPmgrBase + 0x20) = 0x80000000;
499     HwReg(gS5L8930XPmgrBase + 0x2C) = 4;
500     HwReg(gS5L8930XPmgrBase + 0x20) = 0;
503     HwReg(gS5L8930XPmgrBase + 0x21C) = 0;
504     HwReg(gS5L8930XPmgrBase + 0x214) = 1;
505     HwReg(gS5L8930XPmgrBase + 0x210) = 0x80000000;
506     HwReg(gS5L8930XPmgrBase + 0x21C) = 4;
507     HwReg(gS5L8930XPmgrBase + 0x210) = 0;
510     HwReg(gS5L8930XPmgrBase + 0x21C) = 0;
511     HwReg(gS5L8930XPmgrBase + 0x214) = 1;
512     HwReg(gS5L8930XPmgrBase + 0x210) = 0x80000000;
513     HwReg(gS5L8930XPmgrBase + 0x21C) = 4;
514     HwReg(gS5L8930XPmgrBase + 0x210) = 0;