Lines Matching refs:HwReg
53 #define HwReg(x) *((volatile unsigned long*)(x))
164 HwReg(gS5L8900XEdgeICBase + EDGEICCONFIG0) = 0;
165 HwReg(gS5L8900XEdgeICBase + EDGEICCONFIG1) = 0;
170 HwReg(gS5L8900XVic0Base + VICINTENCLEAR) = 0xFFFFFFFF;
171 HwReg(gS5L8900XVic1Base + VICINTENCLEAR) = 0xFFFFFFFF;
173 HwReg(gS5L8900XVic0Base + VICINTENABLE) = 0;
174 HwReg(gS5L8900XVic1Base + VICINTENABLE) = 0;
179 HwReg(gS5L8900XVic0Base + VICINTSELECT) = 0;
180 HwReg(gS5L8900XVic1Base + VICINTSELECT) = 0;
185 HwReg(gS5L8900XVic0Base + VICSWPRIORITYMASK) = 0xFFFF;
186 HwReg(gS5L8900XVic1Base + VICSWPRIORITYMASK) = 0xFFFF;
193 HwReg(gS5L8900XVic0Base + VICVECTADDRS + (i * 4)) = (0x20 * 0) + i;
194 HwReg(gS5L8900XVic1Base + VICVECTADDRS + (i * 4)) = (0x20 * 1) + i;
220 HwReg(gS5L8900XVic0Base + VICINTENABLE) = HwReg(gS5L8900XVic0Base + VICINTENABLE) | (1 << 7) | (1 << 6) | (1 << 5);
243 uint32_t current_irq = HwReg(gS5L8900XVic0Base + VICADDRESS);
267 HwReg(gS5L8900XVic0Base + VICADDRESS) = 0;
314 HwReg(gS5L8900XTimerBase + TIMER_COUNTER) = TIMER_STATE_START;
315 HwReg(gS5L8900XTimerBase + TIMER_CONTROL) = 0x7000 | (1 << 6); /* IRQ enable. */
316 HwReg(gS5L8900XTimerBase + TIMER_DATA0) = clock_decrementer; /* Decrementer. */
318 HwReg(gS5L8900XTimerBase + TIMER_COUNTER) = TIMER_STATE_STOP;