pexpert/arm/pe_omap3530.c

60 #define HwReg(x) *((volatile unsigned long*)(x))
102     while (!(HwReg(OMAP3_UART_BASE + LSR) & LSR_THRE))
105     HwReg(OMAP3_UART_BASE + THR) = c;
116     while (!(HwReg(gOmapSerialUartBase + LSR) & LSR_THRE))
119     HwReg(gOmapSerialUartBase + THR) = c;
125     while (!(HwReg(gOmapSerialUartBase + LSR) & LSR_DR)) {
129     return (HwReg(gOmapSerialUartBase + RBR));
149     HwReg(gOmapSerialUartBase + IER) = 0x00;
150     HwReg(gOmapSerialUartBase + LCR) = LCR_BKSE | LCRVAL;
151     HwReg(gOmapSerialUartBase + DLL) = baudDivisor & 0xFF;
152     HwReg(gOmapSerialUartBase + DLM) = (baudDivisor >> 8) & 0xFF;
153     HwReg(gOmapSerialUartBase + LCR) = LCRVAL;
154     HwReg(gOmapSerialUartBase + MCR) = MCRVAL;
155     HwReg(gOmapSerialUartBase + FCR) = FCRVAL;
170     HwReg(INTCPS_MIR(0)) = 0xffffffff;
171     HwReg(INTCPS_MIR(1)) = 0xffffffff;
172     HwReg(INTCPS_MIR(2)) = 0xffffffff;
182     HwReg(INTCPS_CONTROL) = (1 << 0);
208     HwReg(gOmapTimerBase + TLDR) = 0xffffffe0;
209     HwReg(gOmapTimerBase + TCRR) = 0xffffffe0;
211     HwReg(gOmapTimerBase + TPIR) = 232000;
212     HwReg(gOmapTimerBase + TNIR) = -768000;
214     HwReg(gOmapTimerBase + TOCR) = 0;
215     HwReg(gOmapTimerBase + TOWR) = 100;
217     HwReg(gOmapTimerBase + TCLR) = (1 << 6);
222     HwReg(gOmapTimerBase + TISR) = 0x7;
223     HwReg(gOmapTimerBase + TIER) = 0x7;
233     HwReg(gOmapTimerBase + TCLR) = (1 << 0) | (1 << 1) | (2 << 10);
250     uint32_t irq_number = (HwReg(INTCPS_SIR_IRQ)) & 0x7F;
261         HwReg(gOmapTimerBase + TISR) = 0x7;
271         HwReg(INTCPS_CONTROL) = 0x1;
317     return 0xffffffff - (HwReg(gOmapTimerBase + TCRR));
326         HwReg(gOmapTimerBase + TCLR) |= (1 << 0);
328         HwReg(gOmapTimerBase + TCLR) &= ~(1 << 0);
478         HwReg(gOmapPrcmBase + 0xE00 + 0x40) = current_mode->dss_divisor;