pexpert/arm/pe_omap3430.c

72 #define HwReg(x) *((volatile unsigned long*)(x))
114     while (!(HwReg(OMAP3_UART_BASE + LSR) & LSR_THRE))
117     HwReg(OMAP3_UART_BASE + THR) = c;
128     while (!(HwReg(gOmapSerialUartBase + LSR) & LSR_THRE))
131     HwReg(gOmapSerialUartBase + THR) = c;
137     while (!(HwReg(gOmapSerialUartBase + LSR) & LSR_DR)) {
141     return (HwReg(gOmapSerialUartBase + RBR));
161     HwReg(gOmapSerialUartBase + IER) = 0x00;
162     HwReg(gOmapSerialUartBase + LCR) = LCR_BKSE | LCRVAL;
163     HwReg(gOmapSerialUartBase + DLL) = baudDivisor & 0xFF;
164     HwReg(gOmapSerialUartBase + DLM) = (baudDivisor >> 8) & 0xFF;
165     HwReg(gOmapSerialUartBase + LCR) = LCRVAL;
166     HwReg(gOmapSerialUartBase + MCR) = MCRVAL;
167     HwReg(gOmapSerialUartBase + FCR) = FCRVAL;
182     HwReg(INTCPS_MIR(0)) = 0xffffffff;
183     HwReg(INTCPS_MIR(1)) = 0xffffffff;
184     HwReg(INTCPS_MIR(2)) = 0xffffffff;
194     HwReg(INTCPS_CONTROL) = (1 << 0);
220     HwReg(gOmapTimerBase + TLDR) = 0xffffffe0;
221     HwReg(gOmapTimerBase + TCRR) = 0xffffffe0;
223     HwReg(gOmapTimerBase + TPIR) = 232000;
224     HwReg(gOmapTimerBase + TNIR) = -768000;
226     HwReg(gOmapTimerBase + TOCR) = 0;
227     HwReg(gOmapTimerBase + TOWR) = 100;
229     HwReg(gOmapTimerBase + TCLR) = (1 << 6);
234     HwReg(gOmapTimerBase + TISR) = 0x7;
235     HwReg(gOmapTimerBase + TIER) = 0x7;
245     HwReg(gOmapTimerBase + TCLR) = (1 << 0) | (1 << 1) | (2 << 10);
262     uint32_t irq_number = (HwReg(INTCPS_SIR_IRQ)) & 0x7F;
273         HwReg(gOmapTimerBase + TISR) = 0x7;
283         HwReg(INTCPS_CONTROL) = 0x1;
332     return 0xffffffff - (HwReg(gOmapTimerBase + TCRR));
341         HwReg(gOmapTimerBase + TCLR) |= (1 << 0);
343         HwReg(gOmapTimerBase + TCLR) &= ~(1 << 0);