osfmk/i386/mtrr.c

58 } mtrr_state;
277 	bzero((void *)&mtrr_state, sizeof(mtrr_state));
280 	mtrr_state.MTRRcap     = rdmsr64(MSR_IA32_MTRRCAP);
281 	mtrr_state.MTRRdefType = rdmsr64(MSR_IA32_MTRR_DEF_TYPE);
282 	mtrr_state.var_count   = (unsigned int)(mtrr_state.MTRRcap & IA32_MTRRCAP_VCNT);
285 	if (mtrr_state.var_count) {
286 		mtrr_state.var_range = (mtrr_var_range_t *)
288 		                              mtrr_state.var_count);
289 		if (mtrr_state.var_range == NULL)
290 			mtrr_state.var_count = 0;
294 	if (mtrr_state.var_count)
295 		mtrr_get_var_ranges(mtrr_state.var_range,
296 				    mtrr_state.var_count);
299 	if (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)
300 		mtrr_get_fix_ranges(mtrr_state.fix_range);
353 			mtrr_state.MTRRdefType & ~IA32_MTRR_DEF_TYPE_E);
356 		if (mtrr_state.var_count)
357 			mtrr_set_var_ranges(mtrr_state.var_range,
358 					mtrr_state.var_count);
360 		if (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)
361 			mtrr_set_fix_ranges(mtrr_state.fix_range);
365 			mtrr_state.MTRRdefType | IA32_MTRR_DEF_TYPE_E);
434 	match = mtrr_state.MTRRdefType == rdmsr64(MSR_IA32_MTRR_DEF_TYPE);
438 		match = mtrr_state.MTRRcap == rdmsr64(MSR_IA32_MTRRCAP);
442 	if (match && mtrr_state.var_count) {
443 		match = mtrr_check_var_ranges(mtrr_state.var_range,
444 					      mtrr_state.var_count);
448 	if (match && (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)) {
449 		match = mtrr_check_fix_ranges(mtrr_state.fix_range);
502 	    (mtrr_state.MTRRcap & IA32_MTRRCAP_WC) == 0) {
507 	if (address < 0x100000 || mtrr_state.var_count == 0) {
526 	for (i = 0, free_range = NULL; i < mtrr_state.var_count; i++)
528 		vr = &mtrr_state.var_range[i];
592 	for (i = 0; i < mtrr_state.var_count; i++) {
593 		vr = &mtrr_state.var_range[i];
598 			if (--mtrr_state.var_range[i].refcnt == 0) {
726 	for (i = 0; i < mtrr_state.var_count; i++) {
727 		if (!(mtrr_state.var_range[i].mask & IA32_MTRR_PHYMASK_VALID))
729 		base = mtrr_state.var_range[i].base & IA32_MTRR_PHYSBASE_MASK;
730 		type = (uint32_t)(mtrr_state.var_range[i].base & IA32_MTRR_PHYSBASE_TYPE);
731 		length = MASK_TO_LEN(mtrr_state.var_range[i].mask);
737 			mtrr_state.var_range[i].base &=~IA32_MTRR_PHYSBASE_TYPE;
738 			mtrr_state.var_range[i].base |= MTRR_TYPE_WRITECOMBINE;
747 	mtrr_state.MTRRdefType = MTRR_TYPE_WRITECOMBINE;