Lines Matching defs:base
40 uint64_t base; /* in IA32_MTRR_PHYSBASE format */
134 range[i].base = rdmsr64(MSR_IA32_MTRR_PHYSBASE(i));
154 wrmsr64(MSR_IA32_MTRR_PHYSBASE(i), range[i].base);
220 match = range[i].base == rdmsr64(MSR_IA32_MTRR_PHYSBASE(i)) &&
484 DBG("mtrr_range_add base = 0x%llx, size = 0x%llx, type = %d\n",
583 DBG("mtrr_range_remove base = 0x%llx, size = 0x%llx, type = %d\n",
630 range->base = (address & IA32_MTRR_PHYSBASE_MASK) |
645 v_address = range->base & IA32_MTRR_PHYSBASE_MASK;
646 v_type = (uint32_t)(range->base & IA32_MTRR_PHYSBASE_TYPE);
708 uint64_t base;
713 /* Find the local APIC physical base address */
729 base = mtrr_state.var_range[i].base & IA32_MTRR_PHYSBASE_MASK;
730 type = (uint32_t)(mtrr_state.var_range[i].base & IA32_MTRR_PHYSBASE_TYPE);
732 DBG("%d: base: 0x%016llx size: 0x%016llx type: %d\n",
733 i, base, length, type);
734 if (base <= lapic_pbase &&
735 lapic_pbase <= base + length - PAGE_SIZE) {
737 mtrr_state.var_range[i].base &=~IA32_MTRR_PHYSBASE_TYPE;
738 mtrr_state.var_range[i].base |= MTRR_TYPE_WRITECOMBINE;