osfmk/i386/mtrr.c

68 #define DBG(x...)	kprintf(x)
70 #define DBG(x...)
197 	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
217 	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
234 	DBG("VAR -- BASE -------------- MASK -------------- SIZE\n");
236 		DBG(" %02x    0x%016llx  0x%016llx  0x%llx\n", i,
241 	DBG("\n");
243 	DBG("FIX64K_00000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX64K_00000));
244 	DBG("FIX16K_80000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX16K_80000));
245 	DBG("FIX16K_A0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX16K_A0000));
246 	DBG(" FIX4K_C0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_C0000));
247 	DBG(" FIX4K_C8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_C8000));
248 	DBG(" FIX4K_D0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_D0000));
249 	DBG(" FIX4K_D8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_D8000));
250 	DBG(" FIX4K_E0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_E0000));
251 	DBG(" FIX4K_E8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_E8000));
252 	DBG(" FIX4K_F0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_F0000));
253 	DBG(" FIX4K_F8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_F8000));
255 	DBG("\nMTRRcap = 0x%llx MTRRdefType = 0x%llx\n",
343 		DBG("CPU%d PAT: was 0x%016llx\n", get_cpu_number(), pat);
347 		DBG("CPU%d PAT: is  0x%016llx\n",
379 	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
387 	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
395 	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
429 	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
457 		DBG("mtrr_update_cpu() setting MTRR for cpu %d\n",
484 	DBG("mtrr_range_add base = 0x%llx, size = 0x%llx, type = %d\n",
583 	DBG("mtrr_range_remove base = 0x%llx, size = 0x%llx, type = %d\n",
689 	DBG("CPU%d PAT: was 0x%016llx\n", get_cpu_number(), pat);
717 	DBG("mtrr_lapic_cached() on cpu %d, lapic_pbase: 0x%016llx\n",
732 		DBG("%d: base: 0x%016llx size: 0x%016llx type: %d\n",
736 			DBG("mtrr_lapic_cached() matched var: %d\n", i);