Lines Matching refs:lo
196 uint32_t lo;
199 rdmsr(MSR_IA32_APIC_BASE, lo, hi);
200 if ((lo & MSR_IA32_APIC_BASE_EXTENDED) == 0) {
201 lo |= MSR_IA32_APIC_BASE_EXTENDED;
202 wrmsr(MSR_IA32_APIC_BASE, lo, hi);
210 uint32_t lo;
213 rdmsr(LAPIC_MSR(reg), lo, hi);
214 return lo;
246 uint32_t lo;
252 rdmsr(MSR_IA32_APIC_BASE, lo, hi);
253 is_boot_processor = (lo & MSR_IA32_APIC_BASE_BSP) != 0;
254 is_lapic_enabled = (lo & MSR_IA32_APIC_BASE_ENABLE) != 0;
255 is_x2apic = (lo & MSR_IA32_APIC_BASE_EXTENDED) != 0;
256 lapic_pbase = (lo & MSR_IA32_APIC_BASE_BASE);
424 uint32_t lo;
436 rdmsr(MSR_IA32_APIC_BASE, lo, hi);
437 lo &= ~MSR_IA32_APIC_BASE_BASE;
438 lo |= MSR_IA32_APIC_BASE_ENABLE | LAPIC_START;
439 lo |= MSR_IA32_APIC_BASE_ENABLE;
440 wrmsr(MSR_IA32_APIC_BASE, lo, hi);
460 uint32_t lo;
490 rdmsr(MSR_IA32_APIC_BASE, lo, hi);
491 lo &= ~MSR_IA32_APIC_BASE_ENABLE;
492 wrmsr(MSR_IA32_APIC_BASE, lo, hi);