Lines Matching refs:to
152 add r1, r1, r3 @ add to length
194 add r1, r1, r3 @ add to length
198 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache to PoC
214 add r1, r1, r3 @ add to length
234 add r1, r1, r3 @ add to length
255 add r1, r1, r3 @ add to length
283 * These work very hard to not push registers onto the stack and to limit themselves
284 * to use r0-r3 and ip.
289 mcr p15, 2, r0, c0, c0, 0 @ set cache level to L1
294 clz r1, r3 @ number of bits to MSB of way
317 2: dsb @ wait for stores to finish
346 lsl r2, r2, ip @ shift to set position
351 ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
352 clz r2, ip @ number of bits to MSB of way
358 bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
364 bls .Lnext_level_inv @ yes, go to next level
373 and ip, r0, #0x07000000 @ narrow to LoC
375 add r3, r3, #2 @ go to next level
380 mov r0, #0 @ default back to cache level 0
409 lsl r2, r2, ip @ shift to set position
414 ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
415 clz r2, ip @ number of bits to MSB of way
421 bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
427 bls .Lnext_level_wbinv @ yes, go to next level
436 and ip, r0, #0x07000000 @ narrow to LoC
438 add r3, r3, #2 @ go to next level
443 mov r0, #0 @ default back to cache level 0