dev/i386/dis_tables.c

91 	uint_t		it_invalid64:1;		/* opcode invalid in amd64 */
242 #define	MODE_IMPLIED	3	/* constant value implied from opcode */
249  *   "T" - means to Terminate indirections (this is the final opcode)
251  *   "NS" - means "no suffix" which is the operand length suffix of the opcode
253  *   "u" - means the opcode is invalid in IA32 but valid in amd64
254  *   "x" - means the opcode is invalid in amd64, but not IA32
450  *	"decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
506  * 	Decode table for 0x0FC7 opcode
517  *	Decode table for 0x0FC8 opcode -- 486 bswap instruction
1446 #define	REX_B 0x01	/* extends ModRM r_m, SIB base, or opcode reg */
1671 	uint_t ss;		/* scale-factor from opcode */
1865  * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
1890  * 	0 for "opcode imm, r, r_m" or
1891  *	1 for "opcode imm, r_m, r"
1930  * returns non-zero for bad opcode
1947 	uint_t wbit = 0;	/* opcode wbit, 0 is 8 bit, !0 for opnd_size */
1956 	uint_t opcode3;		/* extra opcode bits usually from ModRM byte */
2006 	 * Get one opcode byte and check for zero padding that follows
2111 	 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
2239 	 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
2246 	 * at this point we should have a correct (or invalid) opcode
2373 	 * At this point most instructions can format the opcode mnemonic
2481 	 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
2555 		 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
2806 		/* long seg reg from opcode */
3241 	 * byte (format Ib).  The int 3 instruction (opcode 0xCC),
3243 	 * it is implied by the opcode. It must be converted
3460 isunsigned_op(char *opcode)
3470 	where = opcode + strlen(opcode) - 1;
3471 	while (where > opcode && *where != ' ')