Lines Matching refs:rd
699 /* Avoid compiler warnings when assigning regs[rd] = NULL */
3534 dtrace_dif_subr(uint_t subr, uint_t rd, uint64_t *regs,
3562 regs[rd] = (dtrace_gethrtime() * 2416 + 374441) % 1771875;
3569 regs[rd] = NULL;
3575 regs[rd] = MUTEX_OWNER(&m.mi) != MUTEX_NO_OWNER;
3577 regs[rd] = LOCK_HELD(&m.mi.m_spin.m_spinlock);
3583 regs[rd] = NULL;
3590 regs[rd] = (uintptr_t)MUTEX_OWNER(&m.mi);
3592 regs[rd] = 0;
3598 regs[rd] = NULL;
3603 regs[rd] = MUTEX_TYPE_ADAPTIVE(&m.mi);
3609 regs[rd] = NULL;
3614 regs[rd] = MUTEX_TYPE_SPIN(&m.mi);
3622 regs[rd] = NULL;
3627 regs[rd] = _RW_READ_HELD(&r.ri, tmp);
3634 regs[rd] = NULL;
3639 regs[rd] = _RW_WRITE_HELD(&r.ri);
3645 regs[rd] = NULL;
3650 regs[rd] = _RW_ISWRITER(&r.ri);
3667 *illval = regs[rd];
3672 regs[rd] = NULL;
3700 regs[rd] = NULL;
3716 regs[rd] = dest;
3731 *illval = regs[rd];
3760 regs[rd] = NULL;
3775 regs[rd] = dest;
3791 regs[rd] = NULL;
3833 regs[rd] = count;
3842 regs[rd] = 0;
3864 regs[rd] = rval;
3893 regs[rd] = rval;
3899 regs[rd] = dtrace_speculation(state);
3971 regs[rd] = NULL;
3975 regs[rd] = sz;
3994 for (regs[rd] = NULL; addr < limit; addr++) {
3996 regs[rd] = addr;
4007 regs[rd] = NULL;
4035 regs[rd] = notfound;
4038 regs[rd] = NULL;
4044 regs[rd] = NULL;
4056 regs[rd] = (uintptr_t)addr;
4058 regs[rd] = 0;
4118 regs[rd] = 0;
4138 regs[rd] = len;
4147 for (regs[rd] = notfound; addr != limit; addr += inc) {
4159 regs[rd] = (uintptr_t)(addr - orig);
4164 regs[rd] = (uintptr_t)addr;
4191 regs[rd] = NULL;
4197 regs[rd] = NULL;
4220 regs[rd] = NULL;
4260 regs[rd] = NULL;
4281 regs[rd] = (uintptr_t)dest;
4297 regs[rd] = NULL;
4303 regs[rd] = NULL;
4344 regs[rd] = (uintptr_t)d;
4351 regs[rd] = (tupregs[0].dttk_value >> NBITSMINOR64) & MAXMAJ64;
4353 regs[rd] = (tupregs[0].dttk_value >> NBITSMINOR) & MAXMAJ;
4359 regs[rd] = (uintptr_t)major( (dev_t)tupregs[0].dttk_value );
4366 regs[rd] = tupregs[0].dttk_value & MAXMIN64;
4368 regs[rd] = tupregs[0].dttk_value & MAXMIN;
4374 regs[rd] = (uintptr_t)minor( (dev_t)tupregs[0].dttk_value );
4402 regs[rd] = NULL;
4407 regs[rd] = NULL;
4565 regs[rd] = (uintptr_t)end;
4575 regs[rd] = NULL;
4593 regs[rd] = NULL;
4599 regs[rd] = NULL;
4606 regs[rd] = NULL;
4619 regs[rd] = NULL;
4629 regs[rd] = (uintptr_t)d;
4643 regs[rd] = NULL;
4656 regs[rd] = (uintptr_t)end + 1;
4664 regs[rd] = (uint16_t)tupregs[0].dttk_value;
4666 regs[rd] = DT_BSWAP_16((uint16_t)tupregs[0].dttk_value);
4674 regs[rd] = (uint32_t)tupregs[0].dttk_value;
4676 regs[rd] = DT_BSWAP_32((uint32_t)tupregs[0].dttk_value);
4684 regs[rd] = (uint64_t)tupregs[0].dttk_value;
4686 regs[rd] = DT_BSWAP_64((uint64_t)tupregs[0].dttk_value);
4701 regs[rd] = NULL;
4707 regs[rd] = NULL;
4822 regs[rd] = (uintptr_t)dest;
4834 regs[rd] = NULL;
4840 regs[rd] = NULL;
4935 regs[rd] = (uintptr_t)dest;
4983 regs[rd] = NULL;
5042 regs[rd] = NULL;
5174 regs[rd] = NULL;
5178 inetout: regs[rd] = (uintptr_t)end + 1;
5193 regs[rd] = KERN_FAILURE;
5211 regs[rd] = ret;
5258 uint_t r1, r2, rd;
5274 rd = DIF_INSTR_RD(instr);
5278 regs[rd] = regs[r1] | regs[r2];
5281 regs[rd] = regs[r1] ^ regs[r2];
5284 regs[rd] = regs[r1] & regs[r2];
5287 regs[rd] = regs[r1] << regs[r2];
5290 regs[rd] = regs[r1] >> regs[r2];
5293 regs[rd] = regs[r1] - regs[r2];
5296 regs[rd] = regs[r1] + regs[r2];
5299 regs[rd] = regs[r1] * regs[r2];
5303 regs[rd] = 0;
5306 regs[rd] = (int64_t)regs[r1] /
5313 regs[rd] = 0;
5316 regs[rd] = regs[r1] / regs[r2];
5322 regs[rd] = 0;
5325 regs[rd] = (int64_t)regs[r1] %
5332 regs[rd] = 0;
5335 regs[rd] = regs[r1] % regs[r2];
5340 regs[rd] = ~regs[r1];
5343 regs[rd] = regs[r1];
5407 regs[rd] = (int8_t)dtrace_load8(regs[r1]);
5417 regs[rd] = (int16_t)dtrace_load16(regs[r1]);
5427 regs[rd] = (int32_t)dtrace_load32(regs[r1]);
5437 regs[rd] = dtrace_load8(regs[r1]);
5447 regs[rd] = dtrace_load16(regs[r1]);
5457 regs[rd] = dtrace_load32(regs[r1]);
5467 regs[rd] = dtrace_load64(regs[r1]);
5471 regs[rd] = (int8_t)
5475 regs[rd] = (int16_t)
5479 regs[rd] = (int32_t)
5483 regs[rd] =
5487 regs[rd] =
5491 regs[rd] =
5495 regs[rd] =
5500 regs[rd] = (int8_t)
5504 regs[rd] = (int16_t)
5508 regs[rd] = (int32_t)
5512 regs[rd] =
5516 regs[rd] =
5520 regs[rd] =
5524 regs[rd] =
5529 rval = regs[rd];
5535 regs[rd] = inttab[DIF_INSTR_INTEGER(instr)];
5538 regs[rd] = (uint64_t)(uintptr_t)
5561 regs[rd] = dtrace_dif_variable(mstate, state,
5576 regs[rd] = svar->dtsv_data;
5588 regs[rd] = NULL;
5590 regs[rd] = a + sizeof (uint64_t);
5596 regs[rd] = dtrace_dif_variable(mstate, state, id, 0);
5615 if (regs[rd] == NULL) {
5623 (void *)(uintptr_t)regs[rd], &v->dtdv_type,
5627 dtrace_vcopy((void *)(uintptr_t)regs[rd],
5632 svar->dtsv_data = regs[rd];
5641 regs[rd] = 0;
5651 regs[rd] = 0;
5682 regs[rd] = NULL;
5684 regs[rd] = a + sizeof (uint64_t);
5692 regs[rd] = tmp[CPU->cpu_id];
5719 if (regs[rd] == NULL) {
5728 (void *)(uintptr_t)regs[rd], &v->dtdv_type,
5732 dtrace_vcopy((void *)(uintptr_t)regs[rd],
5739 tmp[CPU->cpu_id] = regs[rd];
5762 regs[rd] = 0;
5767 regs[rd] = (uint64_t)(uintptr_t)dvar->dtdv_data;
5769 regs[rd] = *((uint64_t *)dvar->dtdv_data);
5793 regs[rd] ? DTRACE_DYNVAR_ALLOC :
5811 (void *)(uintptr_t)regs[rd],
5815 dtrace_vcopy((void *)(uintptr_t)regs[rd],
5818 *((uint64_t *)dvar->dtdv_data) = regs[rd];
5825 regs[rd] = (int64_t)regs[r1] >> regs[r2];
5829 dtrace_dif_subr(DIF_INSTR_SUBR(instr), rd,
5849 dtrace_strlen((char *)(uintptr_t)regs[rd],
5856 tupregs[ttop++].dttk_value = regs[rd];
5865 tupregs[ttop].dttk_value = regs[rd];
5905 regs[rd] = 0;
5910 regs[rd] = (uint64_t)(uintptr_t)dvar->dtdv_data;
5912 regs[rd] = *((uint64_t *)dvar->dtdv_data);
5942 regs[rd] ? DTRACE_DYNVAR_ALLOC :
5950 (void *)(uintptr_t)regs[rd], &v->dtdv_type,
5954 dtrace_vcopy((void *)(uintptr_t)regs[rd],
5957 *((uint64_t *)dvar->dtdv_data) = regs[rd];
5975 regs[rd] = NULL;
5981 regs[rd] = ptr;
5986 if (!dtrace_canstore(regs[rd], regs[r2],
5989 *illval = regs[rd];
5997 (void *)(uintptr_t)regs[rd], (size_t)regs[r2]);
6001 if (!dtrace_canstore(regs[rd], 1, mstate, vstate)) {
6003 *illval = regs[rd];
6006 *((uint8_t *)(uintptr_t)regs[rd]) = (uint8_t)regs[r1];
6010 if (!dtrace_canstore(regs[rd], 2, mstate, vstate)) {
6012 *illval = regs[rd];
6015 if (regs[rd] & 1) {
6017 *illval = regs[rd];
6020 *((uint16_t *)(uintptr_t)regs[rd]) = (uint16_t)regs[r1];
6024 if (!dtrace_canstore(regs[rd], 4, mstate, vstate)) {
6026 *illval = regs[rd];
6029 if (regs[rd] & 3) {
6031 *illval = regs[rd];
6034 *((uint32_t *)(uintptr_t)regs[rd]) = (uint32_t)regs[r1];
6038 if (!dtrace_canstore(regs[rd], 8, mstate, vstate)) {
6040 *illval = regs[rd];
6044 if (regs[rd] & 7) {
6046 if (regs[rd] & 3) { /* Darwin kmem_zalloc() called from dtrace_difo_init() is 4-byte aligned. */
6049 *illval = regs[rd];
6052 *((uint64_t *)(uintptr_t)regs[rd]) = regs[r1];
9087 uint_t rd = DIF_INSTR_RD(instr);
9114 if (rd >= nregs)
9115 err += efunc(pc, "invalid register %u\n", rd);
9116 if (rd == 0)
9126 if (rd >= nregs)
9127 err += efunc(pc, "invalid register %u\n", rd);
9128 if (rd == 0)
9142 if (rd >= nregs)
9143 err += efunc(pc, "invalid register %u\n", rd);
9144 if (rd == 0)
9148 DIF_OP_RLDSB - DIF_OP_LDSB, r1, rd);
9161 if (rd >= nregs)
9162 err += efunc(pc, "invalid register %u\n", rd);
9163 if (rd == 0)
9177 if (rd >= nregs)
9178 err += efunc(pc, "invalid register %u\n", rd);
9179 if (rd == 0)
9190 if (rd >= nregs)
9191 err += efunc(pc, "invalid register %u\n", rd);
9192 if (rd == 0)
9201 if (rd != 0)
9207 if (r2 != 0 || rd != 0)
9233 if (rd >= nregs)
9234 err += efunc(pc, "invalid register %u\n", rd);
9239 if (r1 != 0 || r2 != 0 || rd != 0)
9247 if (rd >= nregs)
9248 err += efunc(pc, "invalid register %u\n", rd);
9249 if (rd == 0)
9257 if (rd >= nregs)
9258 err += efunc(pc, "invalid register %u\n", rd);
9259 if (rd == 0)
9268 if (rd >= nregs)
9269 err += efunc(pc, "invalid register %u\n", rd);
9270 if (rd == 0)
9280 if (rd >= nregs)
9281 err += efunc(pc, "invalid register %u\n", rd);
9282 if (rd == 0)
9293 err += efunc(pc, "invalid register %u\n", rd);
9298 if (rd >= nregs)
9299 err += efunc(pc, "invalid register %u\n", rd);
9300 if (rd == 0)
9726 uint_t rd = DIF_INSTR_RD(instr);
9736 srd = rd;