dev/dtrace/dtrace.c

445 	uint_t actv = CPU->cpu_intr_actv >> (LOCK_LEVEL + 1); \
490 		cpu_core[CPU->cpu_id].cpuc_dtrace_illval = addr;	\
500 		cpu_core[CPU->cpu_id].cpuc_dtrace_illval = addr;	\
538 	    &cpu_core[CPU->cpu_id].cpuc_dtrace_flags;			\
553 		cpu_core[CPU->cpu_id].cpuc_dtrace_illval = addr;	\
580 	    &cpu_core[CPU->cpu_id].cpuc_dtrace_flags;			\
595 		cpu_core[CPU->cpu_id].cpuc_dtrace_illval = addr;	\
630 	    &cpu_core[CPU->cpu_id].cpuc_dtrace_flags;			\
645 		cpu_core[CPU->cpu_id].cpuc_dtrace_illval = addr;	\
760 	 * Most counters stored to in probe context are per-CPU counters.
762 	 * arcane that they don't merit per-CPU storage.  If these counters
924 	volatile uintptr_t *illval = &cpu_core[CPU->cpu_id].cpuc_dtrace_illval;
926 	volatile uint64_t *illval = &cpu_core[CPU->cpu_id].cpuc_dtrace_illval;
1019 	flags = (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
1073 			cpu_core[CPU->cpu_id].cpuc_dtrace_illval = kaddr;
1079 			cpu_core[CPU->cpu_id].cpuc_dtrace_illval = taddr;
1163 	flags = (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
1394 	cpu_core[CPU->cpu_id].cpuc_dtrace_flags |= CPU_DTRACE_UPRIV;
1418 	cpu_core[CPU->cpu_id].cpuc_dtrace_flags |= CPU_DTRACE_UPRIV;
1437 	cpu_core[CPU->cpu_id].cpuc_dtrace_flags |= CPU_DTRACE_UPRIV;
1451 	cpu_core[CPU->cpu_id].cpuc_dtrace_flags |= CPU_DTRACE_UPRIV;
1463 	cpu_core[CPU->cpu_id].cpuc_dtrace_flags |= CPU_DTRACE_KPRIV;
1474 	cpu_core[CPU->cpu_id].cpuc_dtrace_flags |= CPU_DTRACE_KPRIV;
1508 		 * any work for this CPU -- it means that there has not been
1509 		 * a dtrace_dynvar() allocation on this CPU (or from this CPU)
1528 			 * rinsing list for some CPU must be non-NULL.)
1563 	 * This prevents a race whereby a CPU incorrectly decides that
1591 	processorid_t me = CPU->cpu_id, cpu = me;
1783 				 * of a conflicting allocation on another CPU.
1895 				 * this CPU.  Unless we have tried all CPUs,
1897 				 * CPU.
1956 				 *	free list by another CPU.
1973 			 * code path, and only one CPU can own the clean list.
2027 	 * The cas has failed.  Either another CPU is adding an element to
2028 	 * this hash chain, or another CPU is deleting an element from this
2532 			 * without having done a prior speculate() on this CPU
2534 			 * CPU.  There's nothing to do -- we just assert that
2546 			 * This speculation is active on one CPU.  If our
2547 			 * buffer offset is non-zero, we know that the one CPU
2549 			 * different CPU from the speculate(), and we must
2612 	 * If we're lucky enough to be the only active CPU on this speculation
2709 	processorid_t cpu = CPU->cpu_id;
2822  * the active CPU is not the specified CPU -- the speculation will be
2867 			 * This speculation is currently active on one CPU.
2869 			 * that CPU must be us (and we leave the state alone).
2871 			 * CPU -- and change the state to indicate that the
2872 			 * speculation is active on more than one CPU.
3015 			cpu_core[CPU->cpu_id].cpuc_dtrace_illval = NULL;
3030 			cpu_core[CPU->cpu_id].cpuc_dtrace_illval = 0;
3116 			    CPU_ON_INTR(CPU)) {
3230 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3253 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3268 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3286 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3297 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3329 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3370 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3400 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3421 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3442 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3463 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3485 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3508 		if (DTRACE_ANCHORED(mstate->dtms_probe) && CPU_ON_INTR(CPU))
3538 	volatile uint16_t *flags = &cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
3540 	volatile uintptr_t *illval = &cpu_core[CPU->cpu_id].cpuc_dtrace_illval;
3542 	volatile uint64_t *illval = &cpu_core[CPU->cpu_id].cpuc_dtrace_illval;
5238 	volatile uint16_t *flags = &cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
5240 	volatile uintptr_t *illval = &cpu_core[CPU->cpu_id].cpuc_dtrace_illval;
5242 	volatile uint64_t *illval = &cpu_core[CPU->cpu_id].cpuc_dtrace_illval;
5674 				a += CPU->cpu_id * sz;
5692 			regs[rd] = tmp[CPU->cpu_id];
5717 				a += CPU->cpu_id * sz;
5739 			tmp[CPU->cpu_id] = regs[rd];
6262 	dtrace_cpu_t *cpu = CPU;
6312 	uint16_t *flags = &cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
6448 	 * Kick out immediately if this CPU is still being born (in which case
6460 	cpuid = CPU->cpu_id;
6461 	onintr = CPU_ON_INTR(CPU);
6839 				    CPU_ON_INTR(CPU)) {
7000 				 * another CPU has beat us to the exit action,
10390 			 * array) on another CPU.
11314  * buffers on a given CPU.  The atomicity of this operation is assured by
11317  * the same CPU.
11345  * on a CPU.  As with dtrace_buffer_switch(), the atomicity of the operation
11354 	buf = &state->dts_buffer[CPU->cpu_id];
11359 		 * but this isn't necessarily true:  the buffer for the CPU
11405 		 * If there is already a buffer allocated for this CPU, it
13509 		 * CPU.  And if we're on the last CPU, we're going to allocate
14215 	 * interrupts here both to record the CPU on which we fired the BEGIN
14216 	 * probe (the data from this CPU will be processed first at user
14217 	 * level) and to manually activate the buffer for this CPU.
14220 	*cpu = CPU->cpu_id;
14239 	 * want each CPU to transition its principal buffer out of the
14240 	 * INACTIVE state.  Doing this assures that no CPU will suddenly begin
14293 	 * to be sure that every CPU has seen it.  See below for the details
14300 	 * By this point, it is impossible for any CPU to be still processing
14303 	 * other CPU in dtrace_buffer_reserve().  This allows dtrace_probe()
14314 	 * return the CPU on which we actually called the END probe.  This
14315 	 * allows user-land to be sure that this CPU's principal buffer is
14321 	*cpu = CPU->cpu_id;
14458 	 * every CPU is out of probe context.
14646 	uint16_t flags = cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
14691 	ent->dtht_illval = cpu_core[CPU->cpu_id].cpuc_dtrace_illval;
14701 		    ((uint64_t *)(uintptr_t)svar->dtsv_data)[CPU->cpu_id];
14709 	uint16_t *flags = &cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
16776 		 * also going to temporarily set our CPU option to denote
16777 		 * the newly configured CPU.
17907 		 * did not take place -- presumably because the given CPU is
18816 		* did not take place -- presumably because the given CPU is
19694 		 * The cpu_core structure consists of per-CPU state available in any context.
19719 			/* FIXME: track CPU configuration a la CHUD Processor Pref Pane. */