Lines Matching refs:value
544 uint64_t value;
577 value = V_BCM1480_HSP_RX_CALENDAR_LEN(CALENDAR_LEN) |
581 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_1),value);
583 value = V_BCM1480_HSP_TX_MAXBURST1(8) |
590 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_1),value);
617 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0));
619 value &= ~(M_BCM1480_HSP_RX_PLL_MULTIPLIER | M_BCM1480_HSP_RX_PLL_DIV_4);
622 value |= V_BCM1480_HSP_RX_PLL_MULTIPLIER(spi4_pllmult*4) | M_BCM1480_HSP_RX_PLL_DIV_4;
625 value |= V_BCM1480_HSP_RX_PLL_MULTIPLIER(spi4_pllmult);
628 value &= ~_SB_MAKEMASK1(1); /* Clear reserved bit */
632 value |= M_BCM1480_HSP_RSTAT_POLARITY;
637 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0),value);
646 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_TRAINING_FMT));
647 value &= ~M_BCM1480_HSP_TX_TXPREFBURSTSZ;
648 value |= V_BCM1480_HSP_TX_TXPREFBURSTSZ(2);
649 value &= ~M_BCM1480_HSP_TX_TXMAXBURSTSZ;
650 value |= V_BCM1480_HSP_TX_TXMAXBURSTSZ(5);
651 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_TRAINING_FMT),value);
652 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_TRAINING_FMT));
663 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_CALIBRATION));
664 value &= ~M_BCM1480_HSP_CAL_STARTCAL2;
665 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_CALIBRATION),value);
667 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_CALIBRATION));
668 value &= ~M_BCM1480_HSP_CAL_NO_CALIB;
669 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_CALIBRATION),value);
678 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0));
679 value &= ~M_BCM1480_HSP_TX_RST_STATCNT;
680 value |= V_BCM1480_HSP_TX_RST_STATCNT(0);
688 value &= ~(M_BCM1480_HSP_TX_PLL_MULTIPLIER | M_BCM1480_HSP_TX_TX_PLL_DIV_4);
691 value |= V_BCM1480_HSP_TX_PLL_MULTIPLIER(spi4_pllmult*4) | M_BCM1480_HSP_TX_TX_PLL_DIV_4;
694 value |= V_BCM1480_HSP_TX_PLL_MULTIPLIER(spi4_pllmult);
702 value |= M_BCM1480_HSP_TX_TSTAT_SLOW_MODE;
706 value &= ~M_BCM1480_HSP_TX_DIP2_ERRLIMIT;
707 value |= V_BCM1480_HSP_TX_DIP2_ERRLIMIT(1);
708 // value |= M_BCM1480_HSP_TX_TSTAT_POLARITY;
711 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0),value);
723 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0));
724 value &= ~M_BCM1480_HSP_TX_PORT_RESET;
725 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0),value);
728 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0));
729 value &= ~M_BCM1480_HSP_RX_PORT_RESET;
730 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0),value);