Lines Matching defs:port
162 * HT port initialization. See Section 13, pp. 479-480.
166 @fn hsp_ht_ram_alloc ( uint32_t port );
168 void hsp_ht_ram_alloc ( uint32_t port )
177 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_0),
182 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_1),
188 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_1),
195 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_2),
200 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_3),
205 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_4),
210 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_5),
214 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_NPC_RAMALLOC),
217 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_RSP_RAMALLOC),
220 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_PC_RAMALLOC),
224 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTCC_RAMALLOC_0),
229 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTCC_RAMALLOC_1),
234 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTCC_RAMALLOC_2),
241 @fn void hsp_ht_ram_alloc ( uint32_t port );
243 void hsp_ht_flow_alloc (uint32_t port)
250 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTIO_RXPHITCNT),
258 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTCC_RXPHITCNT),
265 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTCC_RXPHITCNT),
273 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTIO_TXPHITCNT),
277 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_HTCC_TXPHITCNT),
286 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_PKT_RAMALLOC(0)),
290 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_PKT_RAMALLOC(0)),
294 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_PKT_RXPHITCNT(0)),
297 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_PKT_TXPHITCNT(0)),
336 void hsp_pm_ram_n_flow_alloc(uint32_t port, uint32_t num_active )
432 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_PKT_RAMALLOC(i)),ramalloc[i]);
436 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI_WATERMARK(i)),watermark[i]);
440 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_PKT_RXPHITCNT(i)),phitcnt[i]);
487 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_PKT_RAMALLOC(i)),ramalloc[i]);
491 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_PKT_TXPHITCNT(i)),phitcnt[i]);
498 @fn void hsp_ht_port_link_reset( uint32_t port );
500 void hsp_ht_port_link_reset( uint32_t port )
504 if (port > BCM1480_HT_NUM_PORTS)
506 printf("ht_port_link_reset: Invalid port %d parameter\n");
514 ctrl = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_LDT_BRCMD);
516 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), R_LDT_BRCMD, ctrl);
517 cmd = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), PPB_BRCTL_INTERRUPT_REG);
519 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), PPB_BRCTL_INTERRUPT_REG, cmd);
523 cmd = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), PPB_BRCTL_INTERRUPT_REG);
525 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), PPB_BRCTL_INTERRUPT_REG, cmd);
534 @fn void hsp_spi4_init_port(uint32_t port,
539 void hsp_spi4_init_port(uint32_t port,
571 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CALENDAR_0),v0);
572 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CALENDAR_1),v1);
574 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CALENDAR_0),v0);
575 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CALENDAR_1),v1);
581 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_1),value);
590 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_1),value);
593 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_PORT_INT_EN),
599 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_PORT_INT_EN),
617 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0));
634 "loopback\n", port);
637 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0),value);
646 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_TRAINING_FMT));
651 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_TRAINING_FMT),value);
652 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_TRAINING_FMT));
663 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_CALIBRATION));
665 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_CALIBRATION),value);
667 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_CALIBRATION));
669 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_CALIBRATION),value);
678 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0));
711 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0),value);
723 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0));
725 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0),value);
728 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0));
730 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0),value);
735 @fn uint32_t hsp_ht_reset_errors(uint32_t port);
737 uint32_t hsp_ht_reset_errors(uint32_t port)
744 csr = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), PCI_COMMAND_STATUS_REG);
748 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), PCI_COMMAND_STATUS_REG, csr);
753 csr = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), PPB_IO_STATUS_REG);
757 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), PPB_IO_STATUS_REG, csr);
763 csr = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKCTRL);
765 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKCTRL, csr);
771 csr = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKFREQERR);
774 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKFREQERR, csr);
780 csr = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_ERRHNDL);
782 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_ERRHNDL, csr);
789 uint32_t hsp_ht_enable_sync_flood_on_errors(uint32_t port, uint32_t enable);
791 uint32_t hsp_ht_enable_sync_flood_on_errors(uint32_t port, uint32_t enable)
798 csr = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKCTRL);
807 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKCTRL, csr);
812 csr = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_ERRHNDL);
821 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_ERRHNDL, csr);
829 uint32_t hsp_ht_check_for_errors(uint32_t port);
831 uint32_t hsp_ht_check_for_errors(uint32_t port)
839 reg = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), PCI_COMMAND_STATUS_REG);
846 reg = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), PPB_IO_STATUS_REG);
854 reg = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKCTRL);
860 reg = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_LINKFREQERR);
867 reg = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_BCM1480_HTB_ERRHNDL);
876 uint32_t hsp_spi4_reset_errors(uint32_t port)
878 uint32_t hsp_spi4_reset_errors(uint32_t port)
882 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS),
888 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS),
906 uint32_t hsp_spi4_check_for_errors(uint32_t port)
908 uint32_t hsp_spi4_check_for_errors(uint32_t port)
915 csr = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS) );
922 csr = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS) );