Lines Matching refs:mcidx
722 * bcm1480_auto_timing(mcidx,tdata)
730 * mcidx - memory controller index (0 or 1)
737 static void bcm1480_auto_timing(int mcidx,mcdata_t *mc,csdata_t *tdata)
1274 base = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
1339 if (mcidx > MC_CHAN0) {
1380 base = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx+2));
1390 * BCM1480_MANUAL_TIMING(mcidx,mc)
1397 * mcidx - memory controller index
1404 static void bcm1480_manual_timing(int mcidx,mcdata_t *mc)
1461 base = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
1491 if (mcidx > MC_CHAN0) {
1502 base = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx+2));
2909 int mcidx,csidx;
2930 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_64BIT_CHANNELS; mcidx++) {
2931 int csidx_start = (d->mc[mcidx].dramtype == JEDEC_DDR2) ? 2:1;
2933 if (d->mc[mcidx].flags & MCFLG_NO_ODT_CS) csidx_start = 1;
2935 int num_csint = csidx_start << d->mc[mcidx].csint;
2942 if (d->mc[mcidx].chantype != MC_64BIT_CHAN) continue;
2944 mcbase = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
2978 if (!(d->mc[mcidx].csdata[csidx].flags & CS_PRESENT)) continue;
2985 d->inuse |= (1 << mcidx);
2991 columns = d->mc[mcidx].csdata[csidx].cols;
2992 rows = d->mc[mcidx].csdata[csidx].rows;
2993 banks = d->mc[mcidx].csdata[csidx].banks;
3013 if ( (d->mc[mcidx].chanintlvint == 1) ) {
3034 if ((d->mc[mcidx].csint > 0) && (csidx < num_csint)) {
3036 chipsels = d->mc[mcidx].csint + ttlbits;
3112 if ((d->mc[mcidx].chanintlvint == 1) && (mcidx == 0)) { /* Channel interleaving */
3113 mcbase1 = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx+1));
3142 d->ttlbytes += dimmsize >> d->mc[mcidx].csint;
3194 else if(d->mc[mcidx].chanintlvint == 0) { /* No channel interleaving */
3209 d->ttlbytes += dimmsize >> d->mc[mcidx].csint;
3251 if (d->mc[mcidx].csint > 0) { /* Set memory channel config reg only if able to csintlv */
3253 switch (d->mc[mcidx].csint) {
3255 if (d->mc[mcidx].dramtype == JEDEC_DDR2)
3261 if (d->mc[mcidx].dramtype == JEDEC_DDR2)
3264 if (d->mc[mcidx].highest_cs_present > 5)
3266 else if (d->mc[mcidx].highest_cs_present > 3)
3285 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_64BIT_CHANNELS; mcidx++) {
3293 if (!(d->mc[mcidx].csdata[csidx].flags & CS_PRESENT)) continue;
3319 mcbase = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
3320 mcbase1 = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx+1));
3408 int mcidx,csidx;
3427 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_32BIT_CHANNELS; mcidx++) {
3428 int csidx_start = (d->mc[mcidx].dramtype == JEDEC_DDR2) ? 2:1;
3430 if (d->mc[mcidx].flags & MCFLG_NO_ODT_CS) csidx_start = 1;
3432 int num_csint = csidx_start << d->mc[mcidx].csint;
3439 if (d->mc[mcidx].chantype != MC_32BIT_CHAN) continue;
3441 mcbase = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
3450 if (!(d->mc[mcidx].csdata[csidx].flags & CS_PRESENT)) continue;
3457 d->inuse |= (1 << mcidx);
3463 columns = d->mc[mcidx].csdata[csidx].cols;
3464 rows = d->mc[mcidx].csdata[csidx].rows;
3465 banks = d->mc[mcidx].csdata[csidx].banks;
3486 if ( (d->mc[mcidx].chanintlvint == 1) ) {
3487 switch (mcidx) {
3493 else if ( (d->mc[mcidx].chanintlvint == 2) ) {
3524 if ((d->mc[mcidx].csint > 0) && (csidx < num_csint)) {
3526 chipsels = d->mc[mcidx].csint + ttlbits;
3640 switch (d->mc[mcidx].chanintlvint) {
3648 d->ttlbytes += dimmsize >> d->mc[mcidx].csint;
3667 if ((mcidx == MC_CHAN1) || (mcidx == MC_CHAN3)) break;
3670 (mcidx == MC_CHAN2)) break;
3673 (mcidx == MC_CHAN0)) break;
3676 for(chan_idx=mcidx; chan_idx <= (mcidx+1); chan_idx++) {
3683 d->ttlbytes += dimmsize >> d->mc[mcidx].csint;
3688 for(chan_idx=mcidx; chan_idx <= (mcidx+1); chan_idx++) {
3699 for(chan_idx=mcidx; chan_idx <= (mcidx+1); chan_idx++) {
3709 if (mcidx != MC_CHAN0) break;
3719 d->ttlbytes += dimmsize >> d->mc[mcidx].csint;
3746 if (d->mc[mcidx].csint > 0) { /* Set memory channel config reg only if able to csintlv */
3748 switch (d->mc[mcidx].csint) {
3750 if (d->mc[mcidx].dramtype == JEDEC_DDR2)
3801 int mcidx;
3806 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_MAX_CHANNELS; mcidx++) {
3807 d->mc[mcidx].chanintlvint = 0;
3808 d->mc[mcidx].csint = 0;
3811 mcidx = MC_FIRSTCHANNEL;
3812 while (mcidx < MC_MAX_CHANNELS) {
3815 if ( (d->mc[mcidx].chantype == MC_64BIT_CHAN) && (mcidx > MC_CHAN1) ) break;
3823 if ( (d->cfg_chanintlv_type > MC_NOCHANINTLV) && (mcidx < MC_CHAN3) ) {
3825 if (d->mc[mcidx].csdata[csidx].rows != d->mc[mcidx+1].csdata[csidx].rows) break;
3826 if (d->mc[mcidx].csdata[csidx].cols != d->mc[mcidx+1].csdata[csidx].cols) break;
3827 if (d->mc[mcidx].csdata[csidx].banks != d->mc[mcidx+1].csdata[csidx].banks) break;
3828 if (d->mc[mcidx].csdata[csidx].flags != d->mc[mcidx+1].csdata[csidx].flags) break;
3830 if (d->mc[mcidx].flags != d->mc[mcidx+1].flags) csidx = 0;
3832 d->mc[mcidx].chanintlvint = 1;
3833 d->mc[mcidx+1].chanintlvint = 1; /* Set matching channel as well */
3846 if ( (d->mc[mcidx].cfgcsint > NOCSINTLV) &&
3847 !(d->mc[mcidx].flags & MCFLG_BIGMEM) &&
3848 (d->mc[mcidx].csdata[0].flags & CS_PRESENT) ) {
3850 csidx = (d->mc[mcidx].dramtype == JEDEC_DDR2) ? 2 : 1;
3853 if ( (d->mc[mcidx].csdata[csidx].flags & CS_PRESENT) &&
3854 (d->mc[mcidx].csdata[0].rows == d->mc[mcidx].csdata[csidx].rows) &&
3855 (d->mc[mcidx].csdata[0].cols == d->mc[mcidx].csdata[csidx].cols) &&
3856 (d->mc[mcidx].csdata[0].banks == d->mc[mcidx].csdata[csidx].banks) ) {
3858 if( csidx > d->mc[mcidx].highest_cs_present )
3859 d->mc[mcidx].highest_cs_present = csidx;
3861 csidx = (d->mc[mcidx].dramtype == JEDEC_DDR2) ? csidx+2 : csidx+1;
3865 d->mc[mcidx].csint = 1; /* Use 1 bit for CS interleaving */
3868 d->mc[mcidx].csint = 2; /* Use 2 bits */
3871 d->mc[mcidx].csint = 3; /* Use 3 bits. 64-bit channels only */
3873 default: d->mc[mcidx].csint = 0; /* All others, no CS interleaving */
3877 if (d->mc[mcidx].csint > NOCSINTLV)
3879 mcidx,d->mc[mcidx].csint);
3883 mcidx++;
3892 for (mcidx = 0; mcidx < MC_MAX_CHANNELS; mcidx++) {
3893 d->mc[mcidx].chanintlvint = 2;
4101 int mcidx;
4140 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_MAX_CHANNELS; mcidx++) {
4141 mcbase = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
4172 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_MAX_CHANNELS; mcidx++) {
4176 mcidx, (d->inuse & (1 << mcidx)) ? "in use" : "not in use");
4181 if (!(d->inuse & (1 << mcidx))) continue;
4186 mcbase = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
4192 mc = &(d->mc[mcidx]);
4205 tdata = &(d->mc[mcidx].csdata[csidx]); /* remember for use below */
4208 bcm1480_manual_timing(mcidx,mc);
4211 bcm1480_auto_timing(mcidx,mc,tdata);
4218 if (d->mc[mcidx].chantype == MC_64BIT_CHAN) {
4228 dramtype = d->mc[mcidx].dramtype;
4248 d->mc[mcidx].modebits = dmbits;
4278 bcm1480_jedec_initcmds(mcidx,mc,csmask,0,tdata);
4288 bcm1480_jedec_ddr2_initcmds(mcidx,mc,csmask,lastcs,0,tdata,d);
4291 bcm1480_sgram_initcmds(mcidx,mc,csmask,tdata);
4294 bcm1480_fcram_initcmds(mcidx,mc,csmask,tdata);
4334 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_MAX_CHANNELS; mcidx++) {
4335 if (!(d->inuse & (1 << mcidx))) continue;
4336 if (d->mc[mcidx].flags & MCFLG_ECC_ENABLE) { /* XXX always zero DRAM to make good ECC */
4357 for (mcidx = MC_FIRSTCHANNEL; mcidx < MC_MAX_CHANNELS; mcidx++) {
4358 if (!(d->inuse & (1 << mcidx))) continue;
4359 if (!(d->mc[mcidx].flags & MCFLG_ECC_ENABLE)) { /* ecc not enabled */
4360 mcbase = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));