Lines Matching refs:value
102 #define NO_COOKIE -1 // arbitrary key value
140 // must provide a seed value
413 pkt->pkt[j+0] = 0xde; // the '0xdeadbeef' init value
611 * hardware for final IVC value. Below setting of IVC really
613 * mapping value.
743 uint64_t value;
746 value = (V_BCM1480_PM_MAP_DEST_ID0(0) |
751 WRITECSR(A_BCM1480_PM_PMO_MAPPING, value);
780 uint64_t value;
783 value = (V_BCM1480_PM_MAP_DEST_ID0(0) |
788 WRITECSR(A_BCM1480_PM_PMO_MAPPING, value);
848 uint64_t value;
849 value = READCSR(addr);
850 value &= ~(M_BCM1480_HR_HEADER_PTR); // clear old one
851 value |= V_BCM1480_HR_HEADER_PTR(offset); // set new one
852 WRITECSR(addr, value);
858 uint64_t value;
859 value = READCSR(addr);
861 value |= M_BCM1480_HR_SELECT_PTNUM_TO_TAG;
862 WRITECSR(addr, value);
868 uint64_t value;
869 value = READCSR(addr);
871 value &= ~M_BCM1480_HR_SELECT_PTNUM_TO_TAG;
872 WRITECSR(addr, value);
879 uint64_t value;
881 value = ivc | (0xffULL << 32);
882 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_OP(i), value);
884 value = (V_BCM1480_HR_RULE_TYPE_WORD_OFST_0(0) |
886 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_TYPE(i), value);
888 value = V_BCM1480_HR_ENABLE(1 << (i)) |
894 WRITECSR(hr.base_addr + R_BCM1480_HR_PATH(j), value);
903 uint64_t value;
905 value = ivc | (0xffULL << 32);
906 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_OP(i), value);
908 value = (V_BCM1480_HR_RULE_TYPE_WORD_OFST_0(0) |
910 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_TYPE(i), value);
912 value = V_BCM1480_HR_ENABLE(1 << (i)) |
918 WRITECSR(hr.base_addr + R_BCM1480_HR_PATH(j), value);
927 uint64_t value;
929 value = op | (((uint64_t) en) << 32);
930 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_OP(i), value);
932 value = V_BCM1480_HR_RULE_TYPE_WORD_OFST_0(word_offset);
933 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_TYPE(i), value);
935 value = V_BCM1480_HR_ENABLE(1 << (i)) |
941 WRITECSR(hr.base_addr + R_BCM1480_HR_PATH(j), value);
946 uint64_t value;
947 value = V_BCM1480_HR_PATH_DATA_DEST(3) | // PMI
951 WRITECSR(addr, value);
956 uint64_t value;
957 value = V_BCM1480_HR_PATH_DATA_DEST(tx) | // to this 'tx' port
961 WRITECSR(hr.base_addr + R_BCM1480_HR_PATH_DEFAULT, value);
966 uint64_t value = 0;
969 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_OP(i), value);
970 WRITECSR(hr.base_addr + R_BCM1480_HR_RULE_TYPE(i), value);
971 WRITECSR(hr.base_addr + R_BCM1480_HR_PATH(i), value);
1582 uint64_t value;
1685 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0));
1686 value |= M_BCM1480_HSP_TX_PORT_RESET;
1687 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_SPI4_CFG_0),value);
1688 value = READCSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0));
1689 value |= M_BCM1480_HSP_RX_PORT_RESET;
1690 WRITECSR(A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_SPI4_CFG_0),value);
1733 value = V_BCM1480_HR_HEADER_PTR(0) |
1735 WRITECSR(hr_cfg_addr, value);
1749 value = (V_BCM1480_HSP_TX_NEXT_ADDR_EVEN(0x400000) |
1753 // value = 0;
1755 WRITECSR(tx_next_addr_addr, value);
1758 // value = 0;
1759 value = 0x40000000;
1761 pci_conf_write(BCM1480_LDT_BRIDGE, PCI_MAPREG(1), value); /* POHT = 0x4000_0000 */
1927 printf("ERROR: Bad vc range %d-%d, must include at least one value\n",
1952 printf("ERROR: Bad vc range %d-%d, must include at least one value\n",
2026 printf("for 16-sequential words, with each bit having same value\n");
2370 * Return value: