Lines Matching refs:softc
118 #define SBDUARTWRITE(softc,reg,val) \
119 (SBREADCSR(softc->uart_mode_reg_1),SBWRITECSR(softc->reg,val))
121 #define SBDUARTREAD(softc,reg) \
122 (SBREADCSR(softc->uart_mode_reg_1),SBREADCSR(softc->reg))
128 sb1250_uart_t *softc;
137 softc = (sb1250_uart_t *) KMALLOC(sizeof(sb1250_uart_t),0);
138 if (softc) {
139 softc->uart_mode_reg_1 = probe_a + R_DUART_CHANREG(probe_b,R_DUART_MODE_REG_1);
140 softc->uart_mode_reg_2 = probe_a + R_DUART_CHANREG(probe_b,R_DUART_MODE_REG_2);
141 softc->uart_clk_sel = probe_a + R_DUART_CHANREG(probe_b,R_DUART_CLK_SEL);
142 softc->uart_cmd = probe_a + R_DUART_CHANREG(probe_b,R_DUART_CMD);
143 softc->uart_status = probe_a + R_DUART_CHANREG(probe_b,R_DUART_STATUS);
144 softc->uart_tx_hold = probe_a + R_DUART_CHANREG(probe_b,R_DUART_TX_HOLD);
145 softc->uart_rx_hold = probe_a + R_DUART_CHANREG(probe_b,R_DUART_RX_HOLD);
146 softc->uart_imr = probe_a + R_DUART_IMRREG(probe_b);
147 softc->uart_oprset = probe_a + R_DUART_SET_OPR;
149 softc->uart_speed = CFG_SERIAL_BAUD_RATE;
150 softc->uart_flowcontrol = SERIAL_FLOW_NONE;
152 cfe_attach(drv,softc,NULL,descr);
158 static void sb1250_uart_setflow(sb1250_uart_t *softc)
163 mode1val = SBDUARTREAD(softc,uart_mode_reg_1);
164 mode2val = SBDUARTREAD(softc,uart_mode_reg_2);
166 switch (softc->uart_flowcontrol) {
178 SBDUARTWRITE(softc,uart_mode_reg_1,mode1val);
179 SBDUARTWRITE(softc,uart_mode_reg_2,mode2val);
185 sb1250_uart_t *softc = ctx->dev_softc;
187 SBDUARTWRITE(softc,uart_mode_reg_1,V_DUART_BITS_PER_CHAR_8 | V_DUART_PARITY_MODE_NONE);
188 SBDUARTWRITE(softc,uart_mode_reg_2,M_DUART_STOP_BIT_LEN_1);
189 SBDUARTWRITE(softc,uart_clk_sel, V_DUART_BAUD_RATE(CFG_SERIAL_BAUD_RATE));
190 SBDUARTWRITE(softc,uart_imr, 0); /* DISABLE all interrupts */
191 SBDUARTWRITE(softc,uart_cmd, M_DUART_RX_EN | M_DUART_TX_EN);
192 if (softc->uart_channel == 0) {
193 SBDUARTWRITE(softc,uart_oprset, M_DUART_SET_OPR0 | M_DUART_SET_OPR2); /* CTS and DTR */
196 SBDUARTWRITE(softc,uart_oprset, M_DUART_SET_OPR1 | M_DUART_SET_OPR3); /* CTS and DTR */
198 sb1250_uart_setflow(softc);
205 sb1250_uart_t *softc = ctx->dev_softc;
213 if (!(SBDUARTREAD(softc,uart_status) & M_DUART_RX_RDY)) break;
214 hs_write8(bptr,(SBDUARTREAD(softc,uart_rx_hold) & 0xFF));
225 sb1250_uart_t *softc = ctx->dev_softc;
227 inpstat->inp_status = (SBDUARTREAD(softc,uart_status) & M_DUART_RX_RDY) ? 1 : 0;
234 sb1250_uart_t *softc = ctx->dev_softc;
245 if (!(SBDUARTREAD(softc,uart_status) & M_DUART_TX_RDY)) break;
249 SBDUARTWRITE(softc,uart_tx_hold,b);
259 sb1250_uart_t *softc = ctx->dev_softc;
264 *info = softc->uart_speed;
267 softc->uart_speed = *info;
268 SBDUARTWRITE(softc,uart_clk_sel,
269 V_DUART_BAUD_RATE(softc->uart_speed));
272 *info = softc->uart_flowcontrol;
275 softc->uart_flowcontrol = *info;
276 sb1250_uart_setflow(softc);
287 sb1250_uart_t *softc = ctx->dev_softc;
289 SBDUARTWRITE(softc,uart_cmd, 0);