Lines Matching refs:t8
107 * t8: - - x tmp
392 * Uses a1, t7, t8, t9 (here and by calling sb_core_reset)
407 andi t8,t1,0xf0 # Find out the CAS latency
408 bne t8,0x20,1f
414 andi t8,t3,0xff
415 sll a1,t8,8 # Replicate rd ncdl 4 times
416 or a1,a1,t8
417 sll t8,a1,16
418 or t8,t8,a1
420 or a1,a1,t8
428 andi t8,t2,0xff
429 or a1,a1,t8
433 andi t8,t4,0xff
434 or a1,a1,t8
497 li t8,50
501 bnez t8,1b
502 subu t8,1
660 * Uses a1, t7, t8, t9 (here and by calling sb_core_reset)
676 andi t8,t1,0xf0 # Find out the CAS latency
677 bne t8,0x20,1f
683 andi t8,t4,0xff
684 ble t8,MEMC_CD_THRESHOLD,1f # if (cd <= 128) rd = cd
687 li t8,MEMC_CD_THRESHOLD # else rd = 128
689 1: # t8 is now rd
690 sll a1,t8,8 # .. replicate it 4 times
691 or a1,a1,t8
692 sll t8,a1,16
693 or t8,t8,a1
695 or a1,a1,t8
703 li t8,0
707 andi t8,t4,0xff # else wr = cd - 128
708 sub t8,t8,MEMC_CD_THRESHOLD
709 andi t8,t8,0xff
711 2: # t8 is now wr, a0 is extra bits
712 or a1,a1,t8
715 andi t8,t2,3
716 sll a1,t8,28
717 andi t8,t3,0xf
718 sll t8,t8,24
719 or t8,t8,a1
725 or a1,a1,t8
765 li t8,50
768 bnez t8,1b
769 subu t8,1
903 * uses t8, t9
920 h0: add t8,ra,24 # This is (h1 - h0)
921 andi t8,t8,0x40
922 bne t8,a1,alt_core_reset
926 li t8,(M_SBTS_FC | M_SBTS_CE | M_SBTS_RS) # 2 instructions
927 h1: sw t8,R_SBTMSTATELOW(a0)
938 li t8,(M_SBTS_FC | M_SBTS_CE | M_SBTS_RS) # 2 instructions
939 h2: sw t8,R_SBTMSTATELOW(a0)
943 lw t8, R_SBTMSTATELOW(a0)
944 lw t8, R_SBTMSTATELOW(a0)
945 lw t8, R_SBTMSTATELOW(a0)
948 li t8, (M_SBTS_FC | M_SBTS_CE)
949 sw t8, R_SBTMSTATELOW(a0)
952 lw t8, R_SBTMSTATELOW(a0)
953 lw t8, R_SBTMSTATELOW(a0)
954 lw t8, R_SBTMSTATELOW(a0)
957 li t8, M_SBTS_CE
958 sw t8, R_SBTMSTATELOW(a0)
961 lw t8, R_SBTMSTATELOW(a0)
962 lw t8, R_SBTMSTATELOW(a0)
963 lw t8, R_SBTMSTATELOW(a0)