Lines Matching refs:val
66 enum opsize size, uint32_t val)
73 errval_t r = pci_write_conf_header(addr.d.doubleword, val);
77 VMKIT_PCI_DEBUG("Written to conf header at %u: %x\n", addr.d.doubleword, val);
86 enum opsize size, uint32_t *val)
89 *val = INVALID;
93 errval_t r = pci_read_conf_header(addr.d.doubleword,val);
97 VMKIT_PCI_DEBUG("Read from conf header at %u: %x\n",addr.d.doubleword, *val);
100 *val = INVALID;
158 static void mem_write(struct pci_device *dev, uint32_t addr, int bar, uint32_t val){
161 //VMKIT_PCI_DEBUG("Write access to Pointer register 0x%"PRIx32" value 0x%"PRIx32"\n", addr & ETH_MMIO_MASK(eth), val);
162 if(val){
163 val = vaddr_to_paddr(val);
165 VMKIT_PCI_DEBUG("Translated to value 0x%"PRIx32"\n", val);
170 val = 1;
175 val = 1;
178 uint32_t tdt = val;
201 uint32_t rdt = val;
235 *((uint32_t *)(((uint64_t)(eth->virt_base_addr)) + addr)) = val;
238 static void mem_read(struct pci_device *dev, uint32_t addr, int bar, uint32_t *val){
240 *val = *((uint32_t *)((uint64_t)(eth->virt_base_addr) + addr));
242 VMKIT_PCI_DEBUG("Read access to Pointer register 0x%"PRIu32" value 0x%"PRIx32"\n", addr, *val);
244 if(*val) {
245 *val = host_to_guest((lvaddr_t)val);
247 VMKIT_PCI_DEBUG("Translated to value 0x%"PRIx32"\n", *val);