Lines Matching refs:val
84 guest_msr_area[i].val = 0x0;
323 uint8_t val = *(uint8_t *)(g->msrpm_va + byte_offset);
325 val = (val & ~(0x3 << bit_offset)) | (access_mode << bit_offset);
327 *(uint8_t *)(g->msrpm_va + byte_offset) = val;
329 //printf("MSR: msr %x, byte_offset %lx, bit_offset %x, val %x\n", msr, byte_offset, bit_offset, val);
901 // control if val is 1 or 0, respectively.
902 static inline void vmx_intercept_desc_table_wrf(struct guest *g, int val)
904 assert(val == 0 || val == 1);
908 if (val) {
1359 set_reg_val_by_reg_num (struct guest *g, uint8_t regnum, uint64_t val) {
1362 guest_set_rax(g, val);
1365 guest_set_rcx(g, val);
1368 guest_set_rdx(g, val);
1371 guest_set_rbx(g, val);
1374 guest_set_rsp(g, val);
1377 guest_set_rbp(g, val);
1380 guest_set_rsi(g, val);
1383 guest_set_rdi(g, val);
1412 uint64_t val;
1426 val = amd_vmcb_cr0_rd_raw(&g->vmcb);
1428 err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_CR0, &val);
1437 val = get_reg_val_by_reg_num(g, mod.u.rm);
1445 guest_set_rax(g, val);
1448 guest_set_rcx(g, val);
1451 guest_set_rdx(g, val);
1454 guest_set_rbx(g, val);
1465 amd_vmcb_cr0_wr_raw(&g->vmcb, val);
1467 err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_CR0, val);
1601 static inline void vmx_vmcs_rflags_cf_wrf(struct guest *g, int val) {
1602 assert(val == 0 || val == 1);
1605 if (val) {
2123 uint32_t val;
2155 // fetch the source val if neccessary
2159 val = guest_get_al(g);
2162 val = guest_get_ax(g);
2165 val = guest_get_eax(g);
2194 r = lpc_handle_pio_write(g->lpc, port, size, val);
2197 r = lpc_handle_pio_read(g->lpc, port, size, &val);
2207 val = ~0;
2264 size, val);
2268 size, &val);
2286 r = pci_handle_pio_write(g->pci, port, size, val);
2288 r = pci_handle_pio_read(g->pci, port, size, &val);
2297 val = 0xffffffff;
2306 guest_set_al(g, val);
2309 guest_set_ax(g, val);
2312 guest_set_eax(g, val);
2341 uint64_t val;
2346 val = ((uint64_t)guest_get_edx(g) << 32) | guest_get_eax(g);
2352 amd_vmcb_sysenter_cs_wr(&g->vmcb, val);
2354 err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_SYSENTER_CS, val);
2359 amd_vmcb_sysenter_esp_wr(&g->vmcb, val);
2361 err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_SYSENTER_ESP, val);
2366 amd_vmcb_sysenter_eip_wr(&g->vmcb, val);
2368 err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_SYSENTER_EIP, val);
2373 amd_vmcb_efer_wr_raw(&g->vmcb, val);
2375 err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_EFER_F, val);
2380 amd_vmcb_fs_base_wr(&g->vmcb, val);
2382 err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_FS_BASE, val);
2387 amd_vmcb_gs_base_wr(&g->vmcb, val);
2389 err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_GS_BASE, val);
2394 amd_vmcb_kernel_gs_base_wr(&g->vmcb, val);
2397 amd_vmcb_star_wr(&g->vmcb, val);
2400 amd_vmcb_lstar_wr(&g->vmcb, val);
2403 amd_vmcb_cstar_wr(&g->vmcb, val);
2406 amd_vmcb_sfmask_wr(&g->vmcb, val);
2420 guest_msr_area[msr_index].val = val;
2429 val = amd_vmcb_sysenter_cs_rd(&g->vmcb);
2431 err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_SYSENTER_CS, &val);
2436 val = amd_vmcb_sysenter_esp_rd(&g->vmcb);
2438 err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_SYSENTER_ESP, &val);
2443 val = amd_vmcb_sysenter_eip_rd(&g->vmcb);
2445 err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_SYSENTER_EIP, &val);
2450 val = amd_vmcb_efer_rd_raw(&g->vmcb);
2452 err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_EFER_F, &val);
2457 val = amd_vmcb_fs_base_rd(&g->vmcb);
2459 err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_FS_BASE, &val);
2464 val = amd_vmcb_gs_base_rd(&g->vmcb);
2466 err = invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_GS_BASE, &val);
2471 val = amd_vmcb_kernel_gs_base_rd(&g->vmcb);
2474 val = amd_vmcb_star_rd(&g->vmcb);
2477 val = amd_vmcb_lstar_rd(&g->vmcb);
2480 val = amd_vmcb_cstar_rd(&g->vmcb);
2483 val = amd_vmcb_sfmask_rd(&g->vmcb);
2496 val = 0x0;
2499 val = 0x1; // enable fast-string instructions
2507 val = guest_msr_area[msr_index].val;
2513 guest_set_eax(g, val);
2514 guest_set_edx(g, val >> 32);
2773 decode_mov_dest_val (struct guest *g, uint8_t *code, uint64_t val)
2787 set_reg_val_by_reg_num(g, modrm.u.regop, val);
2846 uint64_t val;
2852 val = decode_mov_src_val(g, code);
2853 r = apic_handle_mmio_write(g->apic, fault_addr, size, val);
2856 r = apic_handle_mmio_read(g->apic, fault_addr, size, &val);
2858 decode_mov_dest_val(g, code, val);
2887 uint64_t val = decode_mov_src_val(g, code);
2889 dev->mem_write(dev, MMIO_MASK(curbar->bytes) & fault_addr, bar_i, val );
2894 uint64_t val;
2896 dev->mem_read(dev, MMIO_MASK(curbar->bytes) & fault_addr, bar_i, (uint32_t*)&val);
2897 decode_mov_dest_val(g, code, val);