skb/programs/decoding_net4_tests.pl

26     assert_translate(region(["IN"], block(0, 1000)), name(["OUT"], 400)),
28     translate_region(S, region(["IN"], block(0, 1000)), Out),
33     assert_translate(region(["IN"], block(0, 1000)), name(["OUT"], 400)),
35     translate_region(S, In, region(["OUT"], block(400, 1400))),
40     assert_translate(region(["IN"], block(0, 1000)), name(["OUT"], 400)),
42     not(translate_region(S, _, region(["OUT"], block(400, 1500)))).
48     translate_region(S, In, region(["OUT"], block(400, 1500))),
54     assert_translate(region(["NEXT"], block(0, 1000)), name(["OUT"], 400)),
56     decodes_region(S, region(["IN"], block(400, 1000)), Out),
62     assert_translate(region(["NEXT"], block(0, 1000)), name(["OUT"], 400)),
64     decodes_region(S, In, region(["OUT"], block(400, 1500))),
70     assert_translate(region(["NEXT"], block(0, 1000)), name(["OUT"], 400)),
71     assert_accept(region(["OUT"], block(0, 10000))),
73     resolves_region(S, In, region(["OUT"], block(400, 1500))),
79     assert_translate(region(["NEXT"], block(0, 1000)), name(["OUT"], 400)),
80     assert_accept(region(["OUT"], block(0, 700))),
82     not(resolves_region(S, _, region(["OUT"], block(400, 1500)))).
88     assert_translate(region(["SOCKET"], block(1000, 2000)), name(["GDDR"], 0)),
89     assert_translate(region(["SOCKET"], block(10000, 11000)), name(["SMPT_IN"], 0)),
92     assert_translate(region(["PCIBUS"], block(5000, 6000)), name(["DRAM"], 0)),
93     assert_accept(region(["DRAM"], block(0, 1000))),
94     assert_accept(region(["GDDR"], block(0, 1000))),
113     assert_accept(region(["DRAM"], block(0, Size))),
115     state_add_free(S0, ["DRAM"], [block(0,Size)], S1),
129     assert_translate(region(["SOCKET"], block(0, Size)), name(["GDDR"], 0)),
130     assert_translate(region(["SOCKET"], block(10000, 11000)), name(["SMPT_IN"], 0)),
133     assert_translate(region(["PCIBUS"], block(0, Size)), name(["DRAM"], 0)),
134     assert_accept(region(["GDDR"], block(0, Size))),
135     assert_accept(region(["DRAM"], block(0, Size))),
137     state_add_free(S0, ["DRAM"], [block(0,Size)], S1),
138     state_add_free(S1, ["GDDR"], [block(0,Size)], S2),
157     assert_translate(region(["SOCKET"], block(Offset, OffsetLimit)), name(["GDDR"], 0)),
159     state_add_free(S0, ["SOCKET"], [block(Offset,OffsetLimit)], S1),
161     assert_translate(region(["SOCKET"], block(10000, 11000)), name(["SMPT_IN"], 0)),
163     assert_translate(region(["PCIBUS"], block(0, Size)), name(["DRAM"], 0)),
164     assert_accept(region(["GDDR"], block(0, Size))),
165     assert_accept(region(["DRAM"], block(0, Size))),
167     state_add_free(S2, ["DRAM"], [block(0,Size)], S3),
168     state_add_free(S3, ["GDDR"], [block(0,Size)], S4),
171     DstRegion = region(["GDDR"], block(0, Limit2M)),
189     %assert_translate(region(["SOCKET"], block(Offset, OffsetLimit)), name(["GDDR"], 0)),
191     state_add_free(S0, ["SOCKET"], [block(Offset,OffsetLimit)], S1),
192     assert_translate(region(["SOCKET"], block(Offset, OffsetLimit)), name(["SMPT_IN"], 0)),
194     assert_translate(region(["PCIBUS"], block(0, Size)), name(["DRAM"], 0)),
195     assert_accept(region(["GDDR"], block(0, Size))),
196     assert_accept(region(["DRAM"], block(0, Size))),
198     state_add_free(S2, ["DRAM"], [block(0,Size)], S3),
199     state_add_free(S3, ["GDDR"], [block(0,Size)], S4),
203     DstRegion = region(["DRAM"], block(0, Limit2M)),
216     assert_accept_node(S0, region(["DRAM"], block(0, Size)), S1),
217     assert_vspace_node(S1, region(["IN"], block(0,Size)), name(["MMU"], 0), S2),
222     DstRegion = region(["DRAM"], block(0, Limit8M)),
239     assert_accept_node(S0, region(["DRAM"], block(0, Size)),S1),
242     assert_vspace_node(S3, region(["IN"], block(0,Size)), name(["SMPT_IN"], 0), S4),
246     DstRegion = region(["DRAM"], block(0, Limit8M)),
254     assert_accept(region(["DRAM"], block(0, Size))),
257     assert_vspace_node(S0, region(["IN"],block(0,Limit)), name(["SMPT_IN"], 0), S1),
268     assert_accept(region(["DRAM"], block(0, Size))),
270     state_add_free(S0, ["DRAM"], [block(0,Size)], S1),
301     Blk = block(0, Limit2G),
313     findall(X,free_list_insert([block(0,19),block(50,100)], block(20,49), X),Li),
318     free_list_insert([block(0,10)], block(11,20), [block(0,20)]),
319     free_list_insert([block(0,10),block(50,100)], block(20,30), [block(0,10),block(20,30), block(50,100)]),
320     free_list_insert([block(0,19),block(50,100)], block(20,49), [block(0,100)]),
321     free_list_insert([block(50,100)], block(200,210), [block(50,100), block(200,210)]),
322     free_list_insert([block(50,100)], block(0,10), [block(0,10), block(50,100)]),
323     free_list_insert([block(50,100)], block(40,49), [block(40,100)]),
324     findall(R, free_list_allocated([block(0,10),block(20,30), block(50,100)], 0, 100, R), RLi),
333     Blk = block(0, Limit2G),
367     Blk = block(0, Limit2G),
373     Reg1 = region(["DRAM"],  block(Base, Limit)),
384     assert_accept(region(["DRAM"], block(0, Size))),
388     state_add_free(S2, ["DRAM"], [block(0,Size)], S3),
390     state_add_free(S3, ["PROC0"], [block(0,Size)], S4),
391     state_add_free(S4, ["PROC1"], [block(0,Size)], S5),
392     assert_translate(S5, region(["PROC0"], block(0, Size)), name(["MMU0"], 0), S6),
393     assert_translate(S6, region(["PROC1"], block(0, Size)), name(["MMU1"], 0), NewS).