Lines Matching refs:Addr
47 findall(root(Addr,Child,mem(LP,HP)),
48 ( rootbridge(Addr,Child,mem(L,H)),
89 root(Addr,childbus(MinBus,MaxBus),mem(LMem,HMem)) = Root,
93 constrain_bus(Granularity, Type, _, Addr,MinBus,MaxBus,LMem,HMem,BusElementListP),
94 devicetree(BusElementListP,buselement(bridge,Addr,secondary(MinBus),RBaseP,RHighP,RSizeP, Type, _, _, _),T),
97 % constrain_bus(Granularity, Type, prefetchable, Addr,MinBus,MaxBus,LMem,HMem,BusElementListP),
98 % devicetree(BusElementListP,buselement(bridge,Addr,secondary(MinBus),RBaseP,RHighP,RSizeP, Type, prefetchable, _, _),TP),
101 % constrain_bus(Granularity, Type, nonprefetchable, Addr,MinBus,MaxBus,LMem,HMem,BusElementListNP),
102 % devicetree(BusElementListNP,buselement(bridge,Addr,secondary(MinBus),RBaseNP,RHighNP,RSizeNP, Type, nonprefetchable, _, _),TNP),
119 subtract(Lista,[buselement(bridge,Addr,_,_,_,_,_,_,_,_)],Pl),
124 % subtract(Lista,[buselement(bridge,Addr,_,_,_,_,_,prefetchable,_,_)],Pl3),
125 % subtract(Pl3,[buselement(bridge,Addr,_,_,_,_,_,nonprefetchable,_,_)],Pl2),
237 buselement(Type,Addr,BAR,Base,High,Size,_,_,_,_) = Node,
285 device(_,Addr,_,_,Class, SubClass, ProgIf,_),bar(Addr,BAR,B,H,_,_,_)
392 ( buselement(device,Addr,BAR,Base,High,Size,_,_,_,_) = H ->
393 assert(currentbar(Addr,BAR,Base,High,Size));
401 ( buselement(device,Addr,BAR,_,_,_,_,_,_,_) = H ->
402 ( currentbar(Addr,BAR,_,_,_) ->
403 retract(currentbar(Addr,BAR,_,_,_));