Lines Matching refs:Addr
29 findall(root(Addr,Child,mem(LP,HP)),
30 ( rootbridge(Addr,Child,mem(L,H)),
103 root(Addr,childbus(MinBus,MaxBus),mem(LMem,HMem)) = Root,
108 constrain_bus(Granularity, Type, prefetchable, Addr,MinBus,MaxBus,LMem,HMem,BusElementListP),
112 devicetree(BusElementListP,buselement(bridge,Addr,secondary(MinBus),RBaseP,RHighP,RSizeP, Type, prefetchable, _, _),TP),
115 constrain_bus(Granularity, Type, nonprefetchable, Addr,MinBus,MaxBus,LMem,HMem,BusElementListNP),
119 devicetree(BusElementListNP,buselement(bridge,Addr,secondary(MinBus),RBaseNP,RHighNP,RSizeNP, Type, nonprefetchable, _, _),TNP),
134 subtract(Lista,[buselement(bridge,Addr,_,_,_,_,_,prefetchable,_,_)],Pl3),
135 subtract(Pl3,[buselement(bridge,Addr,_,_,_,_,_,nonprefetchable,_,_)],Pl2),
239 ( buselement(device,Addr,BAR,Base,High,Size,_,_,_,_) = H ->
240 assert(currentbar(Addr,BAR,Base,High,Size));
248 ( buselement(device,Addr,BAR,_,_,_,_,_,_,_) = H ->
249 ( currentbar(Addr,BAR,_,_,_) ->
250 retract(currentbar(Addr,BAR,_,_,_));
345 ( buselement(device,Addr,BAR,Base,_,_,_,_,_,_) = H,device(_,Addr,_,_,Class, SubClass, ProgIf,_),bar(Addr,BAR,OrigBase,_,_,_,_) ->